Exploiting temporal loads for low latency and high bandwidth memory
S. Kim, N. Vijaykrishnan
págs. 457-466
Topology adaptive network-on-chip design and implementation
T. A. Bartic, J.-Y. Mignolet
págs. 467-472
págs. 473-481
Low-power branch target buffer for application-specific embedded processors
A. Orailoglu, P. Petrov
págs. 482-488
Efficient unified Montgomery inversion with multibit shifting
A. A.-A. Gutub, M. Naseer, E. Savas
págs. 489-498
Low-power variable-length fast Fourier transform processor
T.-D. Chiueh, Y.-T. Lin, P.-Y. Tsai
págs. 499-506
Selective block buffering TLB system for embedded processors
C. Weems, J.-H. Lee, S.-D. Kim
págs. 507-516
págs. 517-526
Signature-monitoring technique based on instruction-bit grouping
K.-L. Leu, Y.-Y. Chen
págs. 527-536
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