págs. 697-703
Three-stage compression approach to reduce test data volume and testing time for IP cores in SOCs
K. Chakrabarty, L. Li
págs. 704-712
Test generation for embedded circuits under the transparent-scan approach
S. M. Reddy, I. Pomeranz
págs. 713-720
págs. 721-722
RTL power estimation in an HDL-based design flow
A. Macii, Miguel Bruno, M. Poncino
págs. 723-730
Enhancing behavioural-level design flows with statistical power estimation capabilities
B. Arts, N. van der Eng, L. Benini
págs. 731-738
Reducing power dissipation of register alias tables in high-performance processors
G. Kucuk, O. Ergin, D. Ponomarev
págs. 739-746
Leakage current aware high-level estimation for VLSI circuits
F. Li, L. He, J. M. Basile
págs. 747-755
Switching activity reduction in embedded systems: a genetic bus encoding approach
V. Catania, G. Ascia
págs. 756-764
Delay bounds based constraint distribution method
D. Auvergne, N. Azemard, P. Maurine, A. Verle, X. Michel
págs. 765-770
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