IEICE transactions on electronics

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  Año 2006, Vol. 89, Número 6

  • Key Technologies for Miniaturization and Power Reduction of Analog-to-Digital Converters for Video Use (INVITED)

    M. Hotta, T. Matsuura

    pág. 664

    

  • Ultra-Low Voltage Analog Integrated Circuits (INVITED)

    S. Chatterjee, Y. Tsividis, P. Kinget

    pág. 673

    

  • RF Passive Components Using Metal Line on Si CMOS (INVITED)

    K. Masu, K. Okada

    pág. 681

    

  • A Reduced-Sample-Rate Sigma-Delta-Pipeline ADC Architecture for High-Speed High-Resolution Applications

    V. Majidzadeh

    pág. 692

    

  • Design of a Small-Offset 12-Bit CMOS DAC Using Weighted Mean Sample-and-Hold Circuit

    M. Uno, S. Kawahito

    pág. 702

    

  • Simultaneous Compensation of RC Mismatch and Clock Skew in Time-Interleaved S/H Circuits

    Z. Liu, M. Furuta, S. Kawahito

    pág. 710

    

  • An Image Rejection Mixer with Al-Based Improved Performance for WCDMA Applications

    E. Takahashi, M. Iwata, M. Murakawa, K. Watanabe, Y. Ueda, K. Takasuka, Y. Kasai, K. Miyashita, H. Sakanashi

    pág. 717

    

  • True 50% Duty-Cycle SSH and SHH SiGe BiCMOS Divide-by-3 Prescalers

    S. C. Tseng, C. Meng, W. Y. Chen

    pág. 725

    

  • Extended Phase Noise Performance in Mutual Negative Resistance CMOS LC Oscillator for Low Supply Voltages

    A. Worapishet

    pág. 732

    

  • A -90 dBc@10 kHz Phase Noise Fractional-N Frequency Synthesizer with Accurate Loop Bandwidth Control Circuit

    Y. Yamada, K. Sogawa, S. Dosho, T. Morie, K. Okamoto

    pág. 739

    

  • A CMOS Clock and Data Recovery Circuit with a Half-Rate Three-State Phase Detector

    C. Y. Yang, Y. Lee, C. H. Lee

    pág. 746

    

  • All-Digital Clock Deskew Buffer with Variable Duty Cycles

    S. K. Kao, S. I. Liu

    pág. 753

    

  • An On-Chip Multi-Channel Rail-to-Rail Signal Monitoring Technique for Sub-100-nm Digital Signal Integrity

    K. Noguchi, M. Nagata

    pág. 761

    

  • A 1 V Low-Noise CMOS Amplifier Using Autozeroing and Chopper Stabilization Technique

    T. Yoshida, Y. Masui, T. Mashimo

    pág. 769

    

  • Modified CMOS Op-Amp with Improved Gain and Bandwidth

    M. Mottaghi Kashtiban, K. Hadidi, A. Khoei

    pág. 775

    

  • An Image-Filtering LSI Processor Architecture for Face/Object Recognition Using a Sorted Projection-Field Model Based on a Merged/Mixed Analog-Digital Architecture

    T. Nakano, M. Matsugu, O. Nomura, T. Morie, K. Korekado

    pág. 781

    

  • MIMO Interconnects Order Reductions by Using the Multiple Point Adaptive-Order Rational Global Arnoldi Algorithm

    C. C. Chu, M. H. Lai, W. S. Feng

    pág. 792

    

  • A Method Using an Averaging Technique for the Analysis and Evaluation of Real Quasi-Resonant Converters

    Y. C. Lin, D. C. Liaw

    pág. 803

    

  • A Study to Realize a CMOS Pipelined Current-Mode A-to-D Converter for Video Applications

    Y. Sugimoto, Y. Gohda, S. Tanaka

    pág. 811

    

  • A Technique to Reduce Power Consumption for a Linear Transconductor

    F. Matsumoto, I. Yamaguchi, A. Yachidate

    pág. 814

    

  • Design of Analog Current-Mode Loser-Take-All Circuit

    M. Asloni, A. Khoei, K. Hadidi

    pág. 819

    

  • Extended-Range High-Resolution FMCW Reflectometry by Means of Electronically Frequency-Multiplied Sampling Signal Generated from Auxiliary Interferometer

    K. Iiyama, M. Yasuda, S. Takamiya

    pág. 823

    

  • Numerical Investigation of Octagonal Photonic Crystal Fibers with Strong Confinement Field

    H. Higa, K. Kaneshima, Y. Namihira, N. Zou

    pág. 830

    

  • A Leakage Reduction Scheme for Sleep Transistors with Decoupling Capacitors in the Deep Submicron Era

    K. Kobayashi, A. Higuchi, H. Onodera

    pág. 838

    

  • Low-Latency Superscalar and Small-Code-Size Microcontroller Core for Automotive, Industrial, and PC-Peripheral Applications

    H. Yamada, K. Hirayanagi, A. Tomita, K. Hagiwara, T. Kataoka, T. Shimura, Y. Sugure, S. Takeuchi, Yasuyuki Abe

    pág. 844

    

  • A Spread-Spectrum Clock Generator Using Fractional-N PLL with an Extended Range SigmaDelta Modulator

    Y. B. Hsieh

    pág. 851

    

  • Reduction of the Intensity Noise by Electric Positive and Negative Feedback in Blue-Violet InGaN Semiconductor Lasers

    Y. Kuwamura, M. Yamada, K. Saeki, E. Teraoka

    pág. 858

    

  • Improvements in the Design of Matrix Distributed Amplifiers

    E. Hamidi, M. Mohammad Taheri

    pág. 861

    

  • Novel First-Order Non-inverting and Inverting Output of All-Pass Filter at the Same Configuration Using ICCII

    H. P. Chen, M. T. Lin, W. S. Yang

    pág. 865

    

  • A CMOS Built-In Current Sensor for IDDQ Testing

    J. B. Kim, S. H. Hong

    pág. 868