IEICE transactions on information and systems

• 

  Año 1997, Vol. 80, Número 9

  • A routing algorithm and generalization for cube-connected cycle networks

    Hao Yung Lo, Jian Da Chen

    págs. 829-836

    

  • TESH: a new hierarchical interconnection network for massively parallel computing

    Vijay K. Jain, Tadasse Ghirmai, Susumu Horiguchi

    págs. 837-846

    

  • FBSF: a new fast packet switching fabric based on multistage interconnection network with multiple outlets

    ByoungSeob Park, SungChun Kim

    págs. 847-853

    

  • The RDT router chip: a versatile router for suporting a distributed shared memory

    Hiroaki Nishi, Ken Ichiro Anjo, Tomohiro Kudoh

    págs. 854-862

    

  • MINC: multistage interconnection network with cache control mechanism

    Toshihiro Hanawa, Takayuki Kamei, Hideki Yasukawa

    págs. 863-870

    

  • Fault-tolerant cube-connected cycles architectures capable of quick broadcasting by using spare circuits

    Nobuo Tsuda

    págs. 871-878

    

  • An efficiently reconfigurable architecture for mesh-arrays with PE and link faults

    Tadayoshi Horita, Itsuo Takanami

    págs. 879-885

    

  • A novel replication technique for detecting and masking failures for parallel software: active parallel replication

    Adel Cherif, Masato Suzuki, Takuya Katayama

    págs. 886-892

    

  • Special-purpose hardware architecture for large scale linear programming

    Shinhaeng Lee, Shinichiro Omachi, Hirotomo Aso

    págs. 893-898

    

  • Adsmith: an object-based distributed shared memory system for networks of workstations

    Wen Yew Liang, Chung Ta King, Feipei Lai

    págs. 899-908

    

  • The object-space parallel processing of the multipass rendering method on the (M? )2 with a distributed-frame buffer system

    Hitoshi Yamauchi, Takayuki Maeda, Hiroaki Kobayashi

    págs. 909-918

    

  • The improved quasi-minimal residual method on massively parallel distributed memory computers

    Tianruo Yang, Hai Xiang Lin

    págs. 919-924

    

  • Interprocessor memory access arbitrating scheme for TCMP type vector supercomputer

    Tadayuki Sakakibara, Katsuyoshi Kitai, Tadaaki Isobe

    págs. 925-932

    

  • Scalable parallel memory architecture with a skew scheme

    Tadayuki Sakkakibara, Katsuyoshi Kitai, Tadaaki Isobe

    págs. 933-941

    

  • Neural computing for the m-way graph partitioning problem

    Taakayuki Saito, Yoshiyasu Takefuji

    págs. 942-947

    

  • Neural network based photometric stereo with a nearby rotational moving light source

    Yuji Iwahori, Robert J. Woodham, Masahiro Ozaki

    págs. 948-957

    

  • Dyck reductions are more powerlful than homomorphic characterizations

    Sadaki Hirose, Satoshi Okawa, Haruhiko Kimura

    págs. 958-961