IEICE transactions on electronics

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  Año 1999, Vol. 82, Número 9

  • A compact model for the current-voltage characteristics of a single electron transistor in the resonant transport mode

    Kenji Natori, Nobuyuki Sano

    págs. 1599-1606

    

  • Multiple-valued inverter using a single-electron-tunneling circuit

    Masamichi Akazawa, Kentarou Kanaami, Takashi Yamada

    págs. 1607-1614

    

  • A multipole-valued hopfield network device using single-electron circuits

    Takashi Yamada, Yoshihito Amemiya

    págs. 1615-1622

    

  • Analog computation using coupled-quantum-dot spin glass

    Nan-Jian Wu, Hassu Lee, Yoshihito Amemiya

    págs. 1623-1629

    

  • Design and analysis of resonant-tunneling-diode (RTD) based high performance memory system

    Tetsuya Uemura, Pinaki Mazumder

    págs. 1630-1637

    

  • Ultra-fast optoelectronic decision circuit using resonant tunneling diodes and a uni-traveling-carrier photodiode

    Kimikazu Sano, Koichi Murata, Tomoyuki Akeyoshi

    págs. 1638-1646

    

  • Compact residue arithmetic multiplier based on the radix-4 signed-diigit multiple-valued arithmetic circuits

    Shugang Wei, Kensuke Shimizu

    págs. 1647-1654

    

  • New non-volatile analog memory circuits using PWM methods

    Shigeo Kinoshita, Takashi Morie, Makoto Nagata

    págs. 1655-1661

    

  • Multiple-valued logic-in-memory VLSI architecture based on floating-gate-MOS pass-transsistor logic

    Takahiro Hanyu, Michitaka Kameyama

    págs. 1662-1668

    

  • A code-division multiplexing technique for efficient data transmission in VLSI systems

    Yasushi Yuminaka, Kazuhiko Itoh, Yoshisato Sasaki

    págs. 1669-1677

    

  • Self-reconstruction of 3D mesh array with 1 1/2-track switches by digital neural circuits

    Itsuo Takanami, Satoru Nakamura, Tadayoshi Horita

    págs. 1678-1686

    

  • Signed-weight arithmetic and its application to a field-programmable digital filter architecture

    Takafumi Aoki, Yoshiki Sawada, Tatsuo Higuchi

    págs. 1687-1698

    

  • Single-chip implementation of a 32-bit motor-drive-specific microcontroller with floating-point unit

    Jin-Cheon Kim, Sang-Hoon Lee, Joo-Hyun Lee

    págs. 1699-1706

    

  • Fast computational architectures to decrease redundant calculations - eliminating redundant digit calculation and excluding useless data

    Makoto Imai, Toshiyuki Nozawa, Masanori Fujibayashi

    págs. 1707-1714

    

  • A compact memory-merged vector-matching circuitry for neuron-MOS associative processor

    Masahiro Konda, Tadashi Shibata, Tadahiro Ohmi

    págs. 1715-1721

    

  • Collision detection VLSI processor for intelligent vehicles using a hierarchically-content-addressable memory

    Masanori Hariyama, Kazuhiro Sasaki, Michitaka Kameyama

    págs. 1722-1729

    

  • Fully-paralell VLSI implementation of vector quantization processor using neuron-MOS technology

    Akira Nakada, Masahiro Konda, Tatsuo Morimoto

    págs. 1730-1738

    

  • Vision chip for very fast detection of motion vectors: design and implementation

    Zheng Li, Kiyoharu Aizawa

    págs. 1739-1748

    

  • A novel computationally adaptive hardware algorithm for video motion estimation

    Vasily G. Moshnyaga

    págs. 1749-1754

    

  • On sensor motion vector estimation with iterative block matching and non-destructive image sensing

    Dwi Handoko, Shoji Kawahito, Yoshiaki Tadokoro

    págs. 1755-1763

    

  • A low-power A/D conversion technique using correlation of moving pictures

    Shoji Kawahito, Junichi Naka, Yoshiaki Tadokoro

    págs. 1764-1771

    

  • Kow-power scheme of NMOS 4-phase dynamic logic

    Bao-Yu Song, Makoto Furuie, Yukihiro Yoshida

    págs. 1772-1776

    

  • A low-power falf-swing clocking scheme for flip-flop with complementary gate and source drive

    Jin-Cheon Kim, Sang-Hoon Lee, Hong June Park

    págs. 1777-1779