Resumen de Parametric Yield Modeling Using Hidden Variable Logistic Regression
Jung Yoon Hwang, Hyun Cheol Lee
Yield modeling is a critical subject in the semiconductor industry and has undergone extensive research. This article proposes a parametric yield modeling method using a novel technique, namely a hidden variable logistic (HVL) regression. Working with process data, HVL regression can be used to provide an accurate target value and specification limits, which are primary concerns in semiconductor manufacturing, for a particular process variable in a manufacturing step. When success is defined as a status that the semiconductor functions correctly, the probability of success for the particular process variable can be estimated simultaneously with the probability of success for the process variables other than the particular variable using HVL regression. The proposed parametric yield modeling is used effectively to identify the critical process variables and deal with missing observations. The authors demonstrate that HVL regression outperforms logistic regression in terms of integrated mean-squared error (IMSE) through Monte Carlo simulation-based investigations. This is an open access article.
