Resumen de Performance estimation for an EDA tool‐based HW/SW co‐verification environment

A.W. Ruan, Y.B. Liao, P. Li, W.-C. Li

• Purpose – With the growing system‐on‐a‐chip (SOC) design complexity, SOC verification has become a major congestion. In this context, efficient and reliable verification environment is requested for SOC design before it is committed to production. The purpose of this paper is to judge whether the hardware and or software (HW/SW) co‐verification environment can handle SOC verification and provide the necessary performance in terms of co‐verification speed and throughput, power and resource consumption, timing analysis, etc.

  Design/methodology/approach – A finite‐impulse‐response filter is utilized as a device‐under‐test to compare pure SW simulation, Modelsim simulator in this case, and HW/SW co‐verification approaches to decide on whether the HW/SW co‐verification environment can do work or not. In addition, the performance of the HW/SW co‐verification environment is estimated based on specifications such as co‐verification speed and throughput, power and resource consumption, and timing analysis.

  Findings – From experiment results, conclusions can be drawn that the more complicated SOC is, the greater the potential speedup of the co‐verification approach over SW simulation is. However, the communication between SW and HW in HW/SW co‐verification system is a major congestion, which may offset the acceleration achieved by moving large computation from the SW to the HW side.

  Originality/value – Performance estimation for the HW/SW co‐verification environment has been conducted in terms of co‐verification speed and throughput, power and resource consumption, timing analysis, etc