Research of tripartite trench termination for power buried‐gate SIT

• Tang Ying ^[1] ; Li Wan-Qing ^[2]
  1. [1] China Jiliang University

     China Jiliang University

     China

     
  2. [2] Hangzhou Dianzi University

     Hangzhou Dianzi University

     China

     
• Localización: Compel: International journal for computation and mathematics in electrical and electronic engineering, ISSN 0332-1649, Vol. 29, Nº 2 (Special Issue: Selected papers from CAC 2008), 2010, págs. 417-422
• Idioma: inglés
• Enlaces
  • Texto completo
• Resumen

  • Purpose – The purpose of this paper is to introduce trench termination for high power buried‐gate static induction transistor (SIT) comprising three parts, which can inhibit the reverse leakage current substantially and paradisaical current. The simplified step‐etching process will also be discussed in detail.

    Design/methodology/approach – For power buried‐gate SIT, the trench termination comprises three grooves, gate electrode etching, mesa‐groove etching and the separated groove, respectively. The simplified step‐etching process is proposed to optimize the traditional technical processing.

    Findings – The tripartite trench termination of power SIT can inhibit the reverse leakage current, improve the gate‐source breakdown and increase the blocking voltage. The step‐etching process which is proposed for the first time, realizes the tripartite trench termination simultaneously which simplifies the traditional processes and is beneficial by protecting the surface of the die. The optimum etched depth of termination is also presented with experimentations.

    Originality/value – The tripartite trench termination of power SIT is novel and the step‐etching process is also proposed for the first time.