The improvement of HEIP immunity using STI engineering at DRAM

• Autores: Seunguk Han, Youngyoun Lee, Yongdoo Kim, Jemin Park, Junhee Lim, Satoru Yamada, Hyeongsun Hong, Kyupil Lee, Gyoyoung Jin, Eunseung Jung
• Localización: Microelectronics reliability, ISSN 0026-2714, Nº. 76-77, 2017, págs. 164-167
• Idioma: inglés
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• Resumen

  • Abstract The increase of standby current of DRAM caused by the HEIP degradation of p-MOSFET and the way to improve the HEIP immunity without the deterioration of performance are reported. The electron trapping at the top region of STI SiN liner is the main cause of the HEIP degradation. To improve the HEIP immunity, several candidates are examined. The large tabbed-gate device and the thicker STI sidewall oxide are not proper for DRAM due to the decreases of Ion and the refresh time, respectively. The thin poly Si liner, which is inserted between the STI sidewall oxide and the SiN liner, acts as an immune layer against the HEIP degradation. So, the poly Si liner scheme can be a good solution to improve the HEIP immunity without the deterioration of DRAM performance.