Border traps and bias-temperature instabilities in MOS devices

• Autores: D.M. Fleetwood
• Localización: Microelectronics reliability, ISSN 0026-2714, Nº. 80, 2018, págs. 266-277
• Idioma: inglés
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• Resumen

  • Abstract An overview of the effects of border traps on device performance and reliability is presented for Si, Ge, SiGe, InGaAs, SiC, GaN, and carbon-based MOS devices that are subjected to bias-temperature stress, with or without exposure to ionizing radiation. Effective border-trap densities and/or energy distributions are estimated using capacitance-voltage hysteresis, low-frequency noise, charge pumping, and other electrical techniques that vary the time scale over which charge exchange between the semiconductor channel and near-interfacial dielectric. Oxygen vacancies and hydrogen impurity complexes are common border traps in a wide variety of systems subjected to bias-temperature stress. Charge trapping and emission tend to dominate observed bias-temperature instabilities for as-processed devices at higher oxide electric fields (> 4–6 MV/cm), and for irradiated devices. Hydrogen diffusion and reactions become relatively more significant in as-processed devices at lower electric fields (< 4–6 MV/cm).