Improving ESD protection of 5 V NMOSFET large array device in 0.4 μm BCD process

• Autores: Shao-Chang Huang, Hung-Wei Chen, Jen-Hang Yang, Mi-Chang Chang
• Localización: Microelectronics reliability, ISSN 0026-2714, Nº. 84, 2018, págs. 48-54
• Idioma: inglés
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• Resumen

  • In the output stage of power ICs, large array devices (LAD) of MOSFETs are usually used to drive a considerable amount of current. Electrostatic discharge (ESD) self-protection capability of LAD is also required. ESD layout rules are usually adopted in low voltage CMOS transistors to improve the ESD performance but with a large layout area. In this paper, a modified RC gate-driven circuit with gate signal control circuit is developed to keep the minimum device layout rule while achieving ESD self-protection. Thus, it results in a very small layout area increment while keeps the LAD operates safely in normal operation and gains good ESD protection level.