Opcode vector: An efficient scheme to detect soft errors in instructions

• Autores: Jorge Martinez, Mert Atamaner, Pedro Reviriego Vasallo, Oguz Ergin, Marco Ottavi
• Localización: Microelectronics reliability, ISSN 0026-2714, Nº. 86, 2018, págs. 92-97
• Idioma: inglés
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• Resumen

  • Bit flips on instructions may affect the execution of the processor depending on the Instruction Set Architecture (ISA) and the location of the flipped bits. Intrinsically, ISAs may detect bit upsets if the errors on the instructions produce exceptions that halt the execution. In this paper, we explore a dynamic checking of the instructions to detect errors before execution. The scheme is based on loading an approximate representation of the instructions based on a vector that identifies the opcodes used in the program in a special purpose register. During execution, instructions are first checked on the register and on a negative an error is detected as the instruction has an opcode that does not correspond to any of the ones used in the program. Since we use an approximate representation, a small number of false positives can occur for erroneous instructions which may still be detected if they lead to a system crash. The proposed opcode vector scheme is compared with the use of a Bloom filter (BF) that has been previously proposed to detect errors on instructions. In both cases, a check can produce false positives but not false negatives. The Bloom filter is built using all the bits in the instruction. On the other hand, the opcode vector uses only a few bits of the instruction. In both cases, the check is combined with a previous error propagation scheme. In the opcode case, this ensures that all errors corrupt the opcode bits while for the BF, the error propagation reduces the number of false positives. The proposed approach has two main benefits. The first one is an increase in the error detection rate as the set of valid instructions is restricted to those used in the program allowing the detection of invalid instructions even if they do not lead to a system crash. The second one is that errors are detected before the crash. This is done at the cost of adding a small register for the vector of opcodes and some control logic. This is significantly simpler than in the case of the BF that needs to compute several hash functions and access several bits on the register to perform the check. We evaluated this approach on binary files of the ARM Cortex M0 core. According to our findings, the proposed vector of opcodes is more effective to detect errors than the BF and its detection rate is less dependent on the program size. Based on those results, it seems that the proposed method can be an interesting option to detect errors in instructions for systems on which a small overhead can be introduced if it improves reliability.