Resumen de Memory disambiguation hardware: a Review
Fernando Castro Rodríguez, Daniel Ángel Chaver Martínez, Luis Piñuel Moreno, Manuel Prieto Matías, Francisco Tirado Fernández
One of the main challenges of modern processor designs is the implementation of scalable and efficient mechanisms to detect memory access order violations as a result of out-of-order execution. Conventional structures performing this task are complex, inefficient and power-hungry. This fact has generated a large body of work on optimizing address-based memory disambiguation logic, namely the load-store queue. In this paper we review the most significant proposals in this research field, focusing on our own contributions.
