In this paper a slightly modification is proposed to the original Wong and Gotos ATA method for the computation of elementary functions in IEEE 754 single precision. The identification of a trade-off leads to the proposition of a different chunk of the mantissa that in turn brings a reduction in the length of the tables. Results are reported for usual elementary functions based on exhaustive simulations. A mixed framework including VHDL and Matlab R is used for those simulations.
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