Resumen de Controller redesign for delay margin improvement
Two important design objectives in feedback control are steady-state error minimization and delay margin maximization. For many practical systems it is not possible to have infinite delay margin and zero steady state error for unit step reference input. This paper proposes a re-design method for controllers initially designed to satisfy the steady-state error requirement. The objective is to make structural changes in the controller so that a lower bound of the delay margin is improved without affecting the steady-state error. The order of the new controller is (ν+1) higher than the order of the original controller, where ν is the number of unstable poles of the plant.
