VLSI design and comparative analysis of several types of fixed and simple precision floating point multipliers

• Jiménez Pérez, Abimael ^[1] ; Gurrola Navarro, Marco Antonio ^[2] ; Valenzuela De la Cruz, Víctor Manuel ^[3] ; Muñoz Gómez, José Antonio ^[2] ; Aguilar Loreto, Omar ^[2]
  1. [1] Universidad Autónoma de Ciudad Juárez

     Universidad Autónoma de Ciudad Juárez

     México

     
  2. [2] Universidad de Guadalajara

     Universidad de Guadalajara

     México

     
  3. [3] Intel Guadalajara

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• Localización: CULCyT: Cultura Científica y Tecnológica, ISSN-e 2007-0411, Vol. 18, Nº. 1, 2021, 20 págs.
• Idioma: inglés
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• Resumen

  • Multiplication is an arithmetic operation that has a meaningful impact on the performance of several real-life applications, such as digital signal and image processing. Analysis and comparison of different types of fixed-point multipliers such as Wallace tree, array, and Booth-2 with truncated and non-truncated versions were included in this design. Fixed-point multipliers were used to design floating-point multipliers through a hardware description language. As a result, area and speed values were analyzed. Booth-2 fixed multiplier with truncation and RCA adders present both the longest delay and the largest area consumption. Wallace tree floating-point multiplier required the smallest area and the shortest delay. The 8-bit versions of fixed-point multipliers were physically synthesized, using the Alliance tools, to obtain the layout of the circuits. The integrated circuits were successfully fabricated in a 0.5-μm CMOS technology.