Energy Efficient Compressor Cell for Low Power Computing

• Upadhyay, Rahul Mani ^[1] ; Chauhan, R. K. ^[1] ; Kumar , Manish ^[1]
  1. [1] University of Technology

     University of Technology

     Rusia

     
• Localización: ADCAIJ: Advances in Distributed Computing and Artificial Intelligence Journal, ISSN-e 2255-2863, Vol. 12, Nº. 1, 2023
• Idioma: inglés
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• Resumen

  • As the use of multimedia devices is rising, power management is becoming a major challenge. Various types of compressors have been designed in this study. Compressor circuits are designed using several circuits of XOR-XNOR gates and multiplexers. XOR-XNOR gate combinations and multiplexer circuits have been used to construct the suggested compressor design. The performance of the proposed compressor circuits using these low-power XOR-XNOR gates and multiplexer blocks has been found to be economical in terms of space and power. This study proposes low-power and high-speed 3-2, 4-2, and 5-2 compressors for digital signal processing applications. A new compressor has also been proposed that is faster and uses less energy than the traditional compressor. The full adder circuit, constructed using various combinations of XOR-XNOR gates, has been used to develop the proposed compressor. The proposed 3-2 compressor shows average power dissipation 571.7 nW and average delay 2.41 nS, 4-2 compressor shows average power dissipation 1235 nW and average delay 2.7 nS while 5-2 compressor shows average power dissipation 2973.50 nW and average delay 3.75 nS.