Head-of-Line Blocking Reduction in Power-Efficient Networks-on-Chip

• Autores: José Vicente Escamilla López
• Directores de la Tesis: Jose Flich Cardo (dir. tes.)
• Lectura: En la Universitat Politècnica de València ( España ) en 2017
• Idioma: español
• Tribunal Calificador de la Tesis: Pedro Juan López Rodríguez (presid.), Juan Luis Aragón Alcaraz (secret.), Olav Lysne (voc.)
• Programa de doctorado: Programa Oficial de Doctorado en Informática
• Materias:
  • Ciencias tecnológicas
    • Tecnología de los ordenadores
      • Arquitectura de ordenadores
• Enlaces
  • Tesis en acceso abierto en: RiuNet
• Resumen

  • Nowadays, thanks to the continuous improvements in the integration scale, more and more cores are added on the same chip, leading to higher system performance. In order to interconnect all nodes, a network-on-chip (NoC) is used, which is in charge of delivering data between cores. However, increasing the number of cores leads to a significant power consumption increase, leading the NoC to be one of the most expensive components in terms of power. Because of this, during the last years, several mechanisms have been proposed to address the NoC power consumption by means of DVFS (Dynamic Voltage and Frequency Scaling) and power-gating strategies. Nevertheless, improvements achieved by these mechanisms are achieved, to a greater or lesser extent, at the cost of system performance, potentially increasing the risk of saturating the network by forming congested points which, in turn, compromise the rest of the system functionality. One side effect is the creation of the "Head-of-Line blocking" effect where congested packets at the head of queues prevent other non-blocked packets from advancing. To address this issue, in this thesis, on one hand, we propose novel congestion control techniques in order to improve system performance by removing the "Head-of-Line" blocking effect. On the other hand, we propose combined solutions adapted to DVFS in order to achieve improvements in terms of performance and power. In addition to this, we propose a path-aware power-gating-based mechanism, which is capable of detecting the flows sharing buffer resources along data paths and perform to switch them off when not needed. With all these combined solutions we can significantly reduce the power consumption of the NoC when compared with state-of-the-art proposals.