Resumen de Probabilistically time-analyzable complex processor designs
Industry developing Critical Real-Time Embedded Systems (CRTES), such as Aerospace, Space, Automotive and Railways, faces relentless demands for increased guaranteed processor performance to support new advanced functionalities without increasing the verification costs and the limited power budget. To cope with those needs, more complex processor designs are required. Unfortunately, CRTES have to go through a thorough functional and timing verification process. Functional correctness verification has to ensure that despite the presence of faults system's safety will not be compromised while timing verification focus on determining the worst-case execution time (WCET) of programs running in the processor. In CRTES it is of great importance deriving trustworthy and tight WCET estimates.
Current generation CRTES based on relatively simple single-core processors are already extremely difficult to verify and with the advent of multicore and manycore platforms this problem will be exacerbated. Multicore contention in the access to shared hardware resources creates a dependence of the execution time of a task with the rest of the tasks running simultaneously and this makes problem of deriving safe WCET estimate worse. Therefore, timing analysis techniques need to include a lot of pessimism when using the advanced hardware features. Probabilistic Timing Analysis (PTA) has emerged recently as a powerful method to derive WCET estimates for critical tasks on relatively complex processors.
In this thesis we propose PTA-compliant hardware solutions to enable the use of more powerful and complex multicore and manycore processor architectures in future CRTES. Hardware solutions include arbitration policies and techniques to manage shared hardware resources (i.e. shared interconnection network and L2 cache), as well as approaches to obtain trustworthy WCET estimates on top of degraded hardware. PTA implemented on top of the proposed time-randomized designs allows modeling the timing behaviour of applications running in the processor in a probabilistical manner and therefore, WCET bounds can be made tighter.
