Resumen de Adaptive and low-complexity microarchitectures for power reduction
Technology and microarchitecture evolution is driving microprocessors towards higher clock frequencies and higher integration scale. These two factors translate into higher power density, which calls for more sophisticated and expensive cooling systems.
Reduction of power dissipation can be very beneficial not only in terms of cooling cost reduction, but also for saving energy or increasing performance for a given thermal solution or extending battery life.
Processors are often designed to achieve high performance for a wide range of applications with different resource requirements. Thus, it is often the case that the resources are underutilized. Hence, we can save energy because resources waste energy while they are idle. In general, the structures are sized in such a way that making them larger hardly increases the performance, but making them smaller may harm the performance for some programs or for some parts of some programs. Thus, there is room to dynamically adapt these structures to cut the energy consumption of those parts that do not contribute to increase performance. Additionally, this type of worst case design requires high complexity power-hungry structures.
This thesis presents new microarchitectural techniques to reduce the energy consumption and complexity of the main microprocessor structures. We propose new cache memory, issue logic, load/store queue and clustered microarchitecture designs, as well as techniques to dynamically resize these structures.
We show that the proposals presented in this dissertation reduce significantly the dynamic and leakage energy by means of low complexity structures and resizing mechanisms.
