Functional and timing in-hardware verification of fpga-based designs using unit testing frameworks

• Autores: Julián Caba Jiménez
• Directores de la Tesis: Fernando Rincon Calle (dir. tes.), Julio Daniel Dondo Gazzano (dir. tes.), José Ángel Olivas Varela (tut. tes.)
• Lectura: En la Universidad de Castilla-La Mancha ( España ) en 2018
• Idioma: español
• Tribunal Calificador de la Tesis: Juan Carlos López López (presid.), Pablo Pedro Sánchez Espeso (secret.), María Liz Crespo (voc.)
• Programa de doctorado: Programa de Doctorado en Tecnologías Informáticas Avanzadas por la Universidad de Castilla-La Mancha
• Materias:
  • Ciencias tecnológicas
    • Tecnología de los ordenadores
      • Arquitectura de ordenadores
• Enlaces
  • Tesis en acceso abierto en: RUIdeRA
• Resumen

  • Nowadays, high-level modelling is becoming more and more popular to build new hardware designs, providing an early understanding of the design impact decisions, and allowing a more effective design space exploration, which results in a higher design productivity and improves the likelihood of finding the optimal implementation. However, the verification stage still entails an amount of non-trivial problems, such as the following: the trade-off between simulation effort and simulation accuracy completely depends on the design abstraction levels; each testing-level stage induces rewriting tests, which is time-consuming and prone to human errors; the time spent in verification accounts for roughly 60% of the development life-cycle. This task is therefore considered as the bottleneck of most projects; the synthesis consumption-time of a hardware design is too high and has third-party dependencies.

    This dissertation proposes a hardware verification framework using the new generation tools provided by FPGA vendors, whose verification accuracy is close to a real scenario, considering functional and timing factors. In addition, a transparent and remote testing service is provided to automate the verification stage. This service is composed by a hardware platform where a Design Under Test (DUT) is deployed into a dynamically reconfigurable area. DUTs are generated using High-Level Synthesis (HLS) tools, and are verified through unit testing, checking its behavioural and timing correctness. These tests are the same at any abstraction level. The testing process is transparently automated; an engineer commits his design code and unit tests written in a high-level language, such as C, into a repository, and automatically the testing service is able to synthesise the design code, deploy the DUT remotely into a Field-Programmable Gate Array (FPGA) and exercise it with the original unit tests, reporting the testing result to the engineer. In addition, we provide some facilities to reduce third-party dependencies and to increase the intermediate results.