Development and certification of mixed-criticality embedded systems based on probabilistic timing analysis

• Autores: Irune Agirre Troncoso
• Directores de la Tesis: Francisco J. Cazorla (dir. tes.), Mikel Azkarate Askasua Blazquez (codir. tes.)
• Lectura: En la Universitat Politècnica de Catalunya (UPC) ( España ) en 2018
• Idioma: español
• Tribunal Calificador de la Tesis: Guillem Bernat Nicolau (presid.), Miquel Moretó Planas (secret.), Daniel Gracia Pérez (voc.)
• Programa de doctorado: Programa de Doctorado en Arquitectura de Computadores por la Universidad Politécnica de Catalunya
• Materias:
  • Ciencias tecnológicas
    • Tecnología de los ordenadores
      • Arquitectura de ordenadores
      • Sistemas en tiempo real
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• Resumen

  • An increasing variety of emerging systems relentlessly replaces or augments the functionality of mechanical subsystems with embedded electronics. For quantity, complexity, and use, the safety of such subsystems is an increasingly important matter. Accordingly, those systems are subject to safety certification to demonstrate system's safety by rigorous development processes and hardware/software constraints. The massive augment in embedded processors' complexity renders the arduous certification task significantly harder to achieve. The focus of this thesis is to address the certification challenges in multicore architectures: despite their potential to integrate several applications on a single platform, their inherent complexity imperils their timing predictability and certification. Recently, the Measurement-Based Probabilistic Timing Analysis (MBPTA) technique emerged as an alternative to deal with hardware/software complexity. The innovation that MBPTA brings about is, however, a major step from current certification procedures and standards. The particular contributions of this Thesis include: (i) the definition of certification arguments for mixed-criticality integration upon multicore processors. In particular we propose a set of safety mechanisms and procedures as required to comply with functional safety standards. For timing predictability, (ii) we present a quantitative approach to assess the likelihood of execution-time exceedance events with respect to the risk reduction requirements on safety standards. To this end, we build upon the MBPTA approach and we present the design of a safety-related source of randomization (SoR), that plays a key role in the platform-level randomization needed by MBPTA. And (iii) we evaluate current certification guidance with respect to emerging high performance design trends like caches. Overall, this Thesis pushes the certification limits in the use of multicore and MBPTA technology in Critical Real-Time Embedded Systems (CRTES) and paves the way towards their adoption in industry.