Resumen de On the Exploration of FPGAs and High-Level Synthesis Capabilities on Multi-Gigabit-per-Second Networks
Traffic on computer networks has faced an exponential grown in recent years. Both links and communication equipment had to adapt in order to provide a minimum quality of service required for the application. However, in recent years, a few factors have prevented commercial off-the-shelf hardware from being able to keep pace with this growth rate, consequently, some software tools are struggling to fulfill their tasks, especially at speed higher than 10 Gbit/s. For this reason, FPGAs have arisen as an alternative to address the most demanding tasks without the need to create a specific circuit, this is in part to their flexibility and programmability in the field. Needless to say that, developing for FPGAs is well-known to be complex. Therefore, in this thesis we tackle the use of FPGAs and high level synthesis languages in the context of computer networks. We focus on the use of FPGA both in computer network monitoring application and reliable data transmission at very high speeds. On the other hand, we intend to shed light on the use of high level synthesis languages and boost FPGA applicability in the context of computer networks so as to reduce development time and the complexity. In the first part of the thesis, devoted to computer network monitoring. We take advantage of the FPGA determinism in order to implement active monitoring probes, which consist on sending a train of packet which is later used to obtain network parameters. In this case, the determinism is key to reduce the uncertainty of the measurements. The result of our experiments show that the FPGA implementations are much more accurate and are more precise than the software counterpart. At the same time, the FPGA implementation is scalable in terms of network speed --- 1, 10 and 100 Gbit/s. In the context of passive monitoring, we leverage the FPGA architecture to implement algorithms able to thin the cyphered traffic as well as removing duplicate packets. These two algorithms straightforward in principle, but very useful to help traditional network analysis tools to cope with their task at higher network speeds. On one hand, processing cyphered traffic does not bring any benefits, on the other hand, processing duplicate traffic impacts negatively in the performance of the software tools. In the second part of the thesis, devoted to the TCP/IP stack. We explore the current limitation of reliable data transmission at very high speeds. Nowadays, the network is becoming an important bottleneck to fulfill current needs, in particular in datacenters. What is more, in recent years the deployment of 100 Gbit/s network links has started. Consequently, there has been an increase scrutiny of how networking functionality is deployed, furthermore, a wide range of approaches are currently being explored to increase the efficiency of networks and tailor its functionality to the actual needs of the application at hand. FPGAs arise as the perfect alternative to deal with this problem. For this reason, in this thesis we develop Limago an FPGA-based open-source implementation of a TCP/IP stack operating at 100 Gbit/s for Xilinx's FPGAs. Limago not only provides an unprecedented throughput, but also, provides a very small latency when compared to the software implementations, at least fifteen times. Limago is a key contribution in some of the hottest topic at the moment, for instance, network-attached FPGA and In-Network Data Processing.
