Low-power high-resolution cmos switched-capacitor delta-sigma analog-to-digital converters for sensor applications
- Autores: Stepan Sutula
- Directores de la Tesis: Michele Dei (dir. tes.), Francesc Serra Graells (dir. tes.), Carles Ferrer (dir. tes.)
- Lectura: En la Universitat Autònoma de Barcelona ( España ) en 2015
- Idioma: español
- Tribunal Calificador de la Tesis: José Manuel de la Rosa Utrera (presid.), J. Carrabina (secret.), Pieter Rombouts (voc.)
- Materias:
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- Resumen
This PhD thesis explores methods to increase both the power efficiency and the resolution of switched-capacitor Delta-Sigma analog-to-digital converters (ADCs) by employing novel CMOS low-power circuits. A high circuit performance, reliability, low manufacturing costs and a simple design flow to be reused by the scientific community are prioritized.
The Delta-Sigma architecture is chosen because of its simplicity and tolerance for its basic block imperfections. The presented circuit research makes use of switched-capacitor techniques to achieve an appropriate matching between the devices and to be dependent only on the external clock jitter.
The developed low-current analog circuit techniques target power efficiency, taking advantage of the weak- and moderate-inversion regions of the MOS transistor operation. Novel Class-AB operational amplifiers are also investigated as active elements, trying to use energy only for dynamic transitions, thus reducing power consumption at the circuit level. The circuits unused during a certain period of time are switched off, thus reducing power consumption at the system level and minimizing the number of signal-path switching devices.
The circuit reliability is improved by avoiding bootstrapping or other techniques which may increase the operation voltages beyond the nominal supply of the target CMOS technology. Furthermore, the design research also focuses on new circuit topologies with a low sensitivity to both process and temperature deviations in order to increase the yield of the resulting ADCs.
A 96.6-dB-SNDR 50-kHz-BW 1.8-V 7.9-mW Delta-Sigma modulator for ADCs is implemented in a standard 0.18-µm CMOS technology based on the proposed novelties. The measurement results indicate the improvement of the state of the art of high-resolution ADCs without clock bootstrapping, calibration or digital compensation, benefiting a wide range of smart sensing applications.
Another contribution made in the scope of this research work is the improvement of MOS-only single-stage Class-AB operational amplifiers. The developed switched variable-mirror amplifiers, with their remarkable current efficiency and intrinsic frequency compensation together with high full-scale value and open-loop gain, are suitable for low-power high-precision applications extending beyond the specific area of ADCs, such as digital-to-analog converters (DACs), filters or generators.
