Nonlinear control of dc-dc switching converters with constant power load
- Autores: Blanca Areli Martínez Treviño
- Directores de la Tesis: Luis Martínez Salamero (dir. tes.), Abdelali El Aroudi (dir. tes.)
- Lectura: En la Universitat Rovira i Virgili ( España ) en 2019
- Idioma: español
- Tribunal Calificador de la Tesis: Luis Benadero García Morato (presid.), Angel Cid Pastor (secret.), Clara Marina Sanz García (voc.)
- Programa de doctorado: Programa de Doctorado en Tecnologías para Nanosistemas, Bioingeniería y Energía por la Universidad Rovira i Virgili
- Materias:
- Enlaces
- Tesis en acceso abierto en: TDX
- Resumen
Multiconverter systems are usually employed in modern electric vehicles (EV) or dc micro-grids involving a great number of interconnected converters. The key element in these systems is a dc bus, which performs the power distribution to supply both dc and ac loads using the energy provided by the different dc sources, i.e. batteries, fuel cells, photovoltaic generators and ultra-capacitors. Besides the series and parallel connections in both converter ports or in only one of them, and the particular case of paralleling operation due to interleaving, cascade connection is a relevant example of association. Cascade-connection of dc-dc converters arises in many industrial applications such as in modern electric vehicles, sea and undersea vehicles and dc micro-grids. It consists in connecting the output port of the first converter to the input port of the second one. The first stage is called source converter while the second one is denominated load converter. A particular case of the cascade connection is characterized by the operation of the load converter absorbing constant power or, equivalently, by the operation of the source converter supplying a constant power load (CPL). It is well-known that a dc-dc switching converter with ideal regulation at the output, i.e., infinite bandwidth and 100% power conversion efficiency can result in unstable behavior when combined with an input filter section. Several methods have been proposed to cope with the mentioned CPL instability. Moreover, most of the existing contributions are theoretical approaches exploring how to counteract the inherent instability of the CPL. Their main goal has been demonstrating the stabilizing effect of the proposed strategies without showing other important aspects such as rejection to input voltage changes or load variations, inrush current minimization and practical implementation of the control.
The main goal of this research is to describe analytically the cascade connection of converters under constant power supply conditions, and propose simple control solutions that can cope with the potential instability caused by the CPL. With this aim, the use of different strategies such as linear control, slidinf-mode control (SMC), digital SMC (DSMC), and nonlinear PWM control is studied in the regulation of a boost converter supplying a CPL. First,the analysis of the elementary converters in open-loop in the boundary between CCM and DCM carried out in reference is analyzed. Also, the SMC of a boost converter feeding a CPL is exhaustingly covered by a continuous-time approach leading to an analogue implementation. A discrete-time approach for sliding-mode control using a PWM resulting in a digital implementation is presented. Two analogue PWM-based nonlinear controllers as alternative solutions to regulate the output voltage in constant switching frequency operation are proposed. First, the use of a virtual mesh is developed to both stabilize the converter and indirectly regulate the output voltage. Then, a mechanism to estimate the power of the CPL is presented. Finally, the implementation of converters with CPL behavior by presenting a general systematic procedure of synthesis is addressed.
A simple alternative to cope with CPL instabilities has been based on SMC using a linear switching surface to regulate the output voltage of the same converter. The switching surface leads to small values of inrush current and guarantees output voltages regulation in front of external disturbances. The voltage regulation is achieved by adapting the current reference in terms of the input voltage and the power of the CPL making it equal to the expression of the equilibrium point locus. No linearization assumptions have been used in the controller design, this eventually resulting in a good global performance under large-signal operation. The analog SMC proposed in the thesis takes the system as it is, i.e. unstable during both on and off intervals, and exploits the resulting unstable trajectories in each interval to appropriately combine them to obtain a stable system, which exhibits output voltage regulation and small inrush current. It is worth mentioning that only one-loop control is used and no integrators are inserted. While the PWM linear control has been designed in the frequency domain on the basis of a converter averaged linearized model, the SMC design uses the exact trajectories in the phase-plane to reach a compromise between small inrush current and fast output voltage response. This fact is explicit in the SMC approach but it is hidden in the conventional frequency-domain design, which eventually results in a deficient start-up. The analog SMC above described exhibits variable switching frequency because the required switching policy has been implemented by means of hysteresis comparators.
To counteract the variable switching frequency of the analog SMC, a DSMC using PWM has been proposed. The design of the DSMC algorithm has been derived from an approximate discrete-time model of the converter, which predicts accurately the dynamics of the switched system. The DSCM uses a cascade control whose inner loop is a discrete-time sliding-mode control with a switching surface based on the inductor current error, which results in an unstable bahavior. The insertion of the outer loop has stabilized the system and provided output voltage regulation with negligible inrush current. The operation under sliding-mode regime in DSMC approach helps in the inrush current limitation. It has to be pointed out that the presence of propagation delay worsens the inrush current but the problem can be relieved by forcing a non-saturated value of the duty cycle within the few initial switching cycles.
Two non-linear controllers using PWM have been also proposed to solve the problem of regulating the output voltage in a boost converter with CPL under large-signal operation and constant switching frequency. First, the use of state feedback has allowed to stabilize and regulate the output voltage in a virtual mesh. The mesh introduces a damping parameter to stabilize the closed-loop system, and an additional variable to regulate the output voltage. It has been proven by both simulations and experiments that the proposed system exhibits a good performance in the rejection of external perturbations. Secondly, a new strategy with an adaptive loop that estimates the power of CPL has been also proposed showing an excellent performance in the mitigation of the disturbances produced by changes in input voltage and CPL power.
The CPL has been emulated by means of an electronic load and by means of power converters under SMC in Chapter leading to similar results in both cases. Thus, the buck converter has mimicked an instantaneous CPL in two cases, i.e. (i) by changing abruptly its load resistance when the output voltage is regulated by means of a very fast controller, and (ii) by changing the reference power in switching surface that imposes the product of capacitor voltage and inductor current to track such reference by means of an appropriate switching policy. The latter approach has been applied successfully in the input port of boost, Cuk and SEPIC converters, this opening the way to design simple and inexpensive emulations of CPLs.
