Variability-aware design of front-end circuits for self-powered applications
- Autores: Asghar Bahramali
- Directores de la Tesis: María Luisa López Vallejo (dir. tes.)
- Lectura: En la Universidad Politécnica de Madrid ( España ) en 2021
- Idioma: español
- Tribunal Calificador de la Tesis: Carlos Alberto López Barrio (presid.), Andrés Rodríguez Domínguez (secret.), María de Mar Martínez Solórzano (voc.), Ruzica Jevtic (voc.), Ignacio Herrera Alzu (voc.)
- Programa de doctorado: Programa de Doctorado en Ingeniería de Sistemas Electrónicos por la Universidad Politécnica de Madrid
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- Resumen
The advent of electronic engineering has changed human life in the last half century greatly. One of the areas with an ever increasing demand for the use of this branch of engineering is IoT (Internet of Things) applications. There is a wide range of applications in this domain which have been affected deeply by electronic devices. One of the most important areas in the IoT domain where the electronic devices have been used to solve long term important problems are the outdoor battery powered applications. Low power, small area and stability under temperature variations are the crucial requirements for these applications to be covered by the electronic designers.
The characteristic of the electronic domain is such that these requirements can be clearly addressed. Vast usage of CMOS technology with its continual miniaturization trend, low power consumption design techniques and energy autonomous strategies are some of the greatly used approaches in electronic engineering that makes it possible to address low power and low area requirements of IoT applications and the best t for them.
In this work we have provided a self-powered analog platform for applications having the speci c requirements of ultra low power consumption and low area. The platform contains the following blocks: Rectifi er/DC amplifi er, Voltage reference and Regulator. These are the main analog building blocks which are necessary for the small IoT nodes in outdoor applications. To meet low power consumption and low area requisites our strategy has been to design an state-of-the-art sub-threshold biased CMOS-only resistor-less platform.
In designing of these blocks we made two important decisions for applications where power constraint is of great concern. On the one hand we have made use of an external RFID based power harvesting hub that transfers the harvested energy to the desired application through an antenna. On the other hand we have tried to follow state-of-the-art techniques that result in circuit con figurations that are not power hungry.
The main blocks of the proposed analog platform include circuit configurations that contain only regular CMOS devices and are biased in the sub-threshold region of operation. Resistors are avoided mainly because ultra low power consumption requires very large resistances which would occupy much of the chip area. We have used only regular CMOS devices which have the same threshold voltages. In this manner there is no need to use special devices which are not provided by all foundries and make the fabrication process more complicated and less cost effective.
We have realized our design in a commercial 40 nm technology. In this manner not only the design size will be reduced but also it helps to decrease the circuit power consumption. Realizing analog circuits in deep sub-micron technologies makes it also possible to be embedded with digital circuits and to provide a more robust and reliable mixed mode design.
The Dickson charge pump is an integral part of this platform that not only amplifies and rectifies the RFID harvested power but also aids to produce a voltage reference which is temperature resilient. Thermal stability has been achieved taking advantage of the positive temperature coefficient of the Dickson charge pump, being this a main contribution of this PhD Thesis.
The platform is equipped with three voltage references to cover nearly all range of applications. In particular a 1.224V voltage reference provides great dynamic range for the related applications. It is suitable to be used for the temperature range of -10 ºC to 125 ºC with an acceptable TC of 60 (ppm/ºC). The 7 nW power consumption of the reference part of the circuit is low enough to be considered for low power applications. The circuit also takes up a very small area of 330 μm2 (including the charge pump). A 0.365 V voltage reference is suitable for applications where sampling low voltages is required. The proposed configuration benefits from a pre-regulator stage to improve its line regulation. With this strategy the circuit line regulation is 7.5% with PSRR of -73 dB. The circuit has very low active area of 397μm2 (including the charge pump) and a low power consumption of 13.28 nW. The TC of 53 ppm/ºC in the wide temperature range of -55 ºC to 125ºC makes it suitable for IoT outdoor applications. Finally, a mid-bandgap voltage reference that provides 0.570 mV sacrifice power (151.1 nW) to provide a voltage reference with improved line regulation (5 %) and better temperature stability (40 ppm/ºC) in the wide temperature range of -55 ºC to 125 ºC It is suitable in applications where accuracy is of great concern. All voltage references are designed in a two-stage configuration that benefits from an embedded Dickson charge pump both as the supply voltage and as an inherent PTAT voltage.
The last main block of the platform is an all embedded CMOS-only capacitor-less 1.1 V LDO regulator in 40 nm technology with the minimum feasible voltage drop of 200 mV and 800 nA quiescent current witch is 0.08 % of the maximum 1 mA that can be delivered to the load while the output voltage is regulated. Therefore the efficiency of the regulator is 84.6 %. The proposed circuit is based on a standard two-stage amplifier which has the best line regulation among the possible available configurations. The circuit is modified with simple state-of-the-art techniques using minimum device count to provide better performance in two areas of temperature resiliency and load transition performance.
The last main block of the platform is a 1.1V LDO linear regulator with the minimum feasible voltage drop of 200 mV and 800 nA quiescent current witch is 0.08 % of the maximum 1 mA that can be delivered to the load while the output voltage is regulated. Therefore the efficiency of the regulator is 84.6 %. The proposed circuit is based on a standard two-stage amplifier which has the best line regulation among the possible available configurations. The circuit is modified with simple state-of-the-art techniques using minimum device count to provide better performance in two areas of temperature resiliency and load transition performance. The whole circuit consisting of the embedded voltage reference, the Miller and load capacitances take less than 0.007 mm2 of the die size with 1 μW power consumption.
