Analytical modeling of ultrashort-channel mos transistors
- Autores: Ali Kerim Yilmaz
- Directores de la Tesis: François Lime (dir. tes.), Alexander Gunther Klös (dir. tes.)
- Lectura: En la Universitat Rovira i Virgili ( España ) en 2022
- Idioma: español
- Tribunal Calificador de la Tesis: David Jimenez Jimenez (presid.), Antonio Ramon Lázaro Guillén (secret.), Jean-Michel Salles (voc.)
- Programa de doctorado: Programa de Doctorado en Tecnologías para Nanosistemas, Bioingeniería y Energía por la Universidad Rovira i Virgili
- Materias:
- Enlaces
- Tesis en acceso abierto en: TDX
- Resumen
More than six decades ago, in 1959, the first metal-oxide-semiconductor field-effect transistor (MOSFET) was developed at Bell Labs [1-2] in parallel to the first monolithic integrated circuit (IC) at Fairchild Semiconductor [3]. Since then, scientists have been working on miniaturization and optimization of transistor parameters to achieve ICs with higher density and ever better performance with each new technology node. However, for more than a decade, the downscaling of transistors has more and more been confronted with its technological and physical limits. The presence of parasitic short-channel effects (SCEs) due to the emerging loss of gate-control over the channel is a big issue and negatively affects the functionality of MOSFETs, mainly by increasing the subthreshold leakage current and thus degrading the switching performance of the device. In addition to material improvements [4-5], the transition from planar 2-D to 3-D technology was necessary to surround the MOSFET channel with gate material from multiple sides and thus to provide enhanced electrostatic control of the channel.
The tri-gate fin field-effect transistor (FinFET) technology ensured further MOSFET scaling, but once again, the limits of miniaturization are being reached more and more, so the next revolutionary step will happen very soon. The best suppression of SCEs can be achieved by a complete encapsulation of the channel area with gate material. Even though the cylindrical gate-all-around (GAA) nanowire (NW) FET is considered as the ultimate transistor structure among multiple-gate (MG) transistors, GAA nanosheet (NS) FETs are currently preferred because of their comparative simpler manufacturing and greater current yield due to the larger channel area. However, both device structures are of great interest and will shape future technology nodes.
Unfortunately, when the channel length reaches single-digit nanometer dimensions due to the strong scaling, unwanted quantum mechanical effects (QMEs) appear in addition to SCEs. Thin body transistors are confronted with quantum confinement (QC) in the transverse direction and in ultrashort-channel transistors the direct source-to-drain tunneling (DSDT) effect appears in the direction of current transport. The influence of both QMEs on the current characteristics is very different. QC mainly reduces the ON and OFF current and increases the threshold voltage (VT), while DSDT mainly affects the subthreshold region by increasing the subthreshold swing and degrading the drain-induced-barrier-lowering (DIBL).
At these dimensions, fluctuations of some atomic layers can already have a very large influence on the device performance. Therefore, it is of great interest to predict the impacts of each parameter changes on the transistor behavior before production, so that the desired improvements can be made through sensible choices. Technology Computer-Aided Design (TCAD) process and device simulation software are very helpful tools for this purpose and enable a better understanding of the device behavior by providing deeper insight into physical properties. TCAD simulations are computationally very demanding, but not only save high manufacturing costs, but also a lot of time. Nevertheless, today’s microchips consist of billions of transistors, and thus circuit simulations require extremely fast, but also highly accurate physics-based compact models, which are validated by TCAD simulations or measurement results on test wafers.
Although solutions for NW FETs can be found in the literature [6-9], in general, the development of two-dimensional (2-D) analytically closed-form solutions is much easier. Our research group has already developed a unified potential solution based on double-gate (DG) FETs, which is applicable to different transistor types [10]. Hence, one objective of this thesis is to extend this collection by transferring the 2-D analytical potential solution of DG FETs to cylindrical NW FETs with an equivalent dimensions concept. This adapted DG model must consider both SCEs and QMEs. The DSDT current in NS FETs is modeled by the application of the wavelet transform.
First, to obtain equations for the equivalent DG dimensions, it is assumed, based on previous evanescent-mode analysis [11], that with except of the channel length, all other dimensions such as oxide and channel thickness remain the same. Since the behavior of the subthreshold current is mainly affected by the potential barrier height, the surface and center potentials (ΦS & ΦC) of short-channel DG and NW FETs are compared in Synopsys TCAD Sentaurus simulations and matched to each other by channel length adjustments. The comparison of these simulations has shown that the center and surface potentials need different equivalent channel lengths, and the conversion factor also changes for different channel and oxide thicknesses.
