Diseño de sensores implantables para la adquisición de señales neurocorticales.
- Autores: Alberto Rodríguez Pérez
- Directores de la Tesis: Manuel Delgado Restituto (dir. tes.), Fernando Manuel Medeiro Hidalgo (tut. tes.)
- Lectura: En la Universidad de Sevilla ( España ) en 2013
- Idioma: español
- Número de páginas: 203
- Tribunal Calificador de la Tesis: Ramón González Carvajal (presid.), Antonio José Acosta Jiménez (secret.), Georges Gielen (voc.), Ricardo Carmona Galán (voc.), Andreas Demosthenous (voc.)
- Materias:
- Enlaces
- Tesis en acceso abierto en: Idus
- Resumen
In the last years, there has been a growing interest in the design of multichannel neurocortical recording interfaces with wireless transmission capabilities for the untethered measurements of brain activity. These interfaces are expected to play a significant role both in clinical (as part of therapeutic procedures in patients with neurological diseases), brain-machine interfaces and neuroscience applications. They are usually implanted together with an array of multielectrodes in the brain of the patients at the cortex level. Each of these electrodes is able to capture the extracellular action potentials of the adjacent neurons. The interface circuitry is responsible of amplifying, filtering and digitizing the neural signals captured by each of these electrodes and of transmitting them wirelessly to an external spot, where they are processed, analyzed and classified. The wireless capabilities of these systems allow to implant them without any cables across the skull, which were a potential focus of infections and future problems. However, making these recording interfaces wireless presents some challenges in the design of the integrated circuitry. As they are implanted below the skull, completely isolated from any external supply source, the use of ultra-low power consumption techniques is mandatory, not only to prevent from harmful effects in the brain, but also to avoid the need for batteries. Thus, by making the power dissipation low, it becomes feasible to use energy harvesting strategies for supplying the implant. Moreover, the area occupation of the implanted electronics should be minimum in order to comply with the reduced area of the electrode sensors.
This thesis aims to contribute to this scenario and presents a multichannel wireless neural sensor array designed in a standard 0.13um CMOS process. It is composed of 64 channels in which neural signals are acquired, filtered, digitized and optionally compressed to reduce the amount of data sent through the wireless link. The system has two transmission modes; in one case the information captured from a selected set of channels is transmitted as uncompressed raw data, in the other, feature vectors are extracted from the detected neural spikes at every channel and transmitted to the external unit for further processing. A single wireless inductive link, inspired in RFID technologies, is used both for powering the implant and for data transfer to/from the external unit. This link uses a 40.68MHz carrier signal and employs On-Off Keying (OOK) modulation for data transfer from the external unit to the implant (forward link) and Load-Shift Keying (LSK) in the reverse direction (backward link). A 4MHz clock is used to send information through the backward link. This is enough for the implant operated in the feature extraction mode to characterize and serialize the detected spikes even in the unlikely case all the channels fire at the same instant. Experimental results show that the total power consumption of the system, including the recording array and the communication protocol, is only 377uW (5.9uW per channel), i.e., about one order of magnitude below prior art. This outstanding performance is achieved through an optimum design of the interface circuits embedded in the channels in terms of both their area and power consumption, an efficient compression of the input neural data and a low-power digital processing. Each of the channels includes all the necessary circuitry to amplify, filter, digitize and compress the input neural data. Specifically, this work presents the design of a bandpass filter and low-noise amplifier that implements the well-known capacitive feedback topology, in which some circuit-level improvements have been introduced to enhance its power/noise performance. Additionally, a dedicated design methodology that is able to map directly the system design constraints into transistor sizes and biasing conditions was used to get an optimum design in terms of power, area and noise. Measurements show that the amplifier and filter stage consumes 1.92uW and the total integrated input-referred noise is just 3.8uVrms, with a bandpass gain of 47.5dB over a bandwidth between 192 Hz and 6.7 kHz. The noise efficiency factor is as low as 2.16. On the other hand, this thesis presents a novel architecture that combines both PGA and ADC functionalities in just one block, thus saving area and power consumption compared to the traditional approaches. It was implemented using a SC-based circuit, which performs a binary search algorithm to complete the conversion. In order to optimize its power consumption, the bias current of the OTA is adapted during the conversion to the changing settling requirements. The ENOB of the ADC is above 7.5 bit for all the gain configurations (0-18 dB in 3-bit steps), while it consumes 1.52uW for a 90kS/s input sampling frequency. It only occupies 0.032mm2 and the energy per conversion is just 85.85 fJ. Besides, several digital power reduction techniques, such as clock gating and optimized clock frequencies, have been used in the digital parts to minimize their power consumption.
