Modeling TCP/IP software implementation performance and its application for software routers

• Autores: Oscar Iván Lepe Aldama
• Directores de la Tesis: Jorge García Vidal (dir. tes.)
• Lectura: En la Universitat Politècnica de Catalunya (UPC) ( España ) en 2004
• Idioma: inglés
• ISBN: 84-688-5817-X
• Depósito Legal: B.14704-2004
• Tribunal Calificador de la Tesis: Ramón Puigjaner Trepat (presid.), Olga M. Casals Torres (secret.), José Francisco Duato Marin (voc.), Joan García Haro (voc.), Sebastià Sallent Ribes (voc.)
• Enlaces
  • Tesis en acceso abierto en: TDX
• Resumen
  • English

    Existen numerosos trabajos que estudian o tratan la realización software de los protocolos de comunicaciones para el acceso a la Internet-TCP/IP. Sin embargo, no conocemos ninguno que modele de forma general y precisa la ejecución de este software.

    La presente tesis aporta una caracterización detallada de la ejecución de la realización software de los mencionados protocolos sobre un computador personal y bajo un sistema operativo UNIX. Esta caracterización muestra cómo varía el rendimiento del sistema en función de la velocidad de operación de la CPU, las características del subsistema de memoria, el tamaño de los paquetes y otras variables de importancia para la remisión, autenticación y cifrado de paquetes IP.

    En otros trabajos se proponen adecuaciones o extensiones a la realización software de los mencionados protocolos que permiten que un software router provea de comunicaciones con diversos niveles asegurados de calidad mediante el uso de mecanismos de planificación para la unidad central de procesamiento. Sin embargo, en dichos trabajos no se contempla la planificación del uso del bus de entrada/salida.

    Los resultados derivados de nuestro modelo demuestran que, para sistemas que usan CPUs con frecuencias de reloj superiores a 1 GHz, la planificación conjunta de la CPU y el bus de entrada salida es indispensable para la provisión de comunicaciones con diversos niveles asegurados de calidad. Dichas frecuencias de reloj son comunes en los sistemas comerciales actuales, por lo que consideramos que es un problema de gran interés. En la tesis proponemos un mecanismo que consigue garantías de utilización del bus de entrada/salida mediante la modificación de los drivers de los interfaces de red.

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  • English

    Three are the main contributions of this work. In no particular order:

    " A detailed performance study of the software implementation of the TCP/IP protocols suite, when executed as part of the kernel of a BSD operating system over generic PC hardware.

    " A validated queuing network model of the studied system, solved by computer simulation.

    " An I/O bus utilization guard mechanism for improving the performance of software routers supporting QoS mechanisms and built upon PC hardware and software.

    This document presents our experiences building a performance model of a PC-based software router. The resulting model is an open multiclass priority network of queues that we solved by simulation. While the model is not particularly novel from the system modeling point of view, in our opinion, it is an interesting result to show that such a model can estimate, with high accuracy, not just average performance-numbers but the complete probability distribution function of packet latency, allowing performance analysis at several levels of detail. The validity and accuracy of the multiclass model has been established by contrasting its packet latency predictions in both, time and probability spaces. Moreover, we introduced into the validation analysis the predictions of a router's single queue model. We did this for quantitatively assessing the advantages of the more complex multiclass model with respect to the simpler and widely used but not so accurate, as here shown, single queue model, under the considered scenario that the router's CPU is the system bottleneck and not the communications links. The single queue model was also solved by simulation.

    Besides, this document addresses the problem of resource sharing in PC-based software routers supporting QoS mechanisms. Others have put forward solutions that are focused on suitably distributing the workload of the CPU-see this chapter's section on "related work". However, the increase in CPU speed in relation to that of the I/O bus-as here shown-means attention must be paid to the effect the limitations imposed by this bus on the system's overall performance. We propose a mechanism that jointly controls both I/O bus and CPU operation. This mechanism involves changes to the operating system kernel code and assumes the existence of certain network interface card's functions, although it does not require changes to the PC hardware. A performance study is shown that provides insight into the problem and helps to evaluate both the effectiveness of our approach, and several software router design trade-offs.