Cache architectures based on heterogeneous technologies to deal with manufacturing errors
- Autores: Vicente Jesús Lorente Garcés
- Directores de la Tesis: Salvador Petit (dir. tes.), Julio Sahuquillo Borras (dir. tes.)
- Lectura: En la Universitat Politècnica de València ( España ) en 2015
- Idioma: inglés
- Tribunal Calificador de la Tesis: María Engracia Gómez Requena (presid.), Manuel Eugenio Acacio Sánchez (secret.), Manuel Pérez Malumbres (voc.)
- Materias:
- Enlaces
- Tesis en acceso abierto en: RiuNet
- Resumen
Static Random-Access Memory (SRAM) technology has traditionally been used to im- plement processor caches since it is the fastest existing RAM technology. However, one of the major drawbacks of this technology is its high energy consumption. To reduce this energy consumption modern processors mainly use two complementary techniques: i) low-power operating modes and ii) low-power memory technologies. The first tech- nique allows the processor working at low clock frequencies and supply voltages. The main limitation of this technique is that manufacturing defects can significantly affect the reliability of SRAM cells when working these modes. The second technique brings alternative technologies such as embedded Dynamic RAM (eDRAM), which provides minimum area and power consumption. The main drawback of this memory technology is that reads are destructive and eDRAM cells work slower than SRAM ones. To ad- dress these design concerns, heterogeneous (SRAM/eDRAM) cache organizations have recently been proposed with the aim of reducing consumption without sacrificing the performance. This thesis presents three main contributions regarding low-power caches and heteroge- neous technologies: i) an study that identifies the optimal capacitance of eDRAM cells, ii) a novel cache design that tolerates the faults produced by SRAM cells in low-power modes, iii) a methodology that allows obtain the optimal operating frequency/voltage level when working with low-power modes. Regarding the first contribution, in this work SRAM and eDRAM technologies are com- bined to achieve a low-power fast cache that requires smaller area than conventional designs and that tolerates SRAM failures. First, this dissertation focuses on one of the main critical aspects of the design of heterogeneous caches: eDRAM cell capacitance. This capacitance affects both the performance and the energy consumption because when the capacitors¿ retention time of the eDRAM cells expires, they lose the stored logic value. In this dissertation the optimal capacitance for an heterogeneous L1 data cache is identified by analyzing the compromise between performance and energy con- sumption. Experimental results show that an heterogeneous cache implemented with 10fF capacitors offers similar performance as a conventional SRAM cache while providing 55% energy savings and reducing by 29% the cache area. Regarding the second contribution, this thesis proposes a novel organization for a fault- tolerant heterogeneous cache. Currently, reducing the supply voltage is a mechanism widely used to reduce consumption and applies when the system workload activity de- creases. However, SRAM cells cause different types of failures when the supply voltage is reduced and thus they limit the minimum operating voltage of the microprocessor. This limitation makes difficult further energy savings, since other parts of the system could correctly work with lower supply voltages. The proposal allows higher reductions on supply voltage than other existing solutions addressing SRAM error detection and correction. In the proposal, memory cells implemented with eDRAM technology serve as backup in case of failure of SRAM cells, because the correct operation of eDRAM cells is not affected by reduced voltages. The proposed architecture has two working modes: high-performance mode for supply voltages that do not induce SRAM cell failures, and low-power mode for those voltages that cause SRAM cell failures. In high-performance mode, the cache provides full capacity, which enables the processor to achieve its max- imum performance. In low-power mode, the effective capacity of the cache is reduced because some of the eDRAM cells are dedicated to recover from SRAM failures. Experi- mental results show that the performance is scarcely reduced (e.g. less than 2.7% across all the studied benchmarks) with respect to an ideal SRAM cache without failures. Finally, this thesis proposes a methodology to find the optimal frequency/voltage level regarding energy consumption for the designed heterogeneous cache. For this purpose, first SRAM failure types and their probabilities are characterized. Then, the energy consumption of different frequency/voltage levels is evaluated when the system works in low-power mode. The study shows that, mainly due to the impact of SRAM failures on performance, the optimal combination of voltage and frequency from the energy point of view does not always correspond to the minimum voltage.
