IEICE transactions on fundamentals of electronics, communications and computer

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  Año 2005, Vol. 88, Número 4

  • Rigorous Verification of Poincaré Map Generated by a Continuous Piece-Wise Linear Vector Field and Its Application

    H. Okazaki

    págs. 810-817

    

  • Optimal Design of Sensor Parameters in PLC-Based Control System Using Mixed Integer Programming

    Eiji Konaka

    págs. 818-824

    

  • Path Following Circuits - SPICE-Oriented Numerical Methods Where Formulas are Described by Circuits-

    Kiyotaka Yamamura

    págs. 825-831

    

  • Rail-to-Rail OTA Utilizing Linear V-I Conversion Circuit Whose Input Stage is Composed of Single Channel MOSFETs

    Nobukazu Takai, Keigo Kawai

    págs. 832-837

    

  • Unified Phase Compiler by Use of 3-D Representation Space

    Takefumi Miyoshi, Nobuhiko Sugino

    págs. 838-845

    

  • Memory Allocation and Code Optimization Methods for DSPs with Indexed Auto-Modificaton

    Yuhei Kaneko, Nobuhiko Sugino, Akinori Nishihara

    págs. 846-854

    

  • A Noise Reduction Method Based on Linear Prediction with Variable Step-Size

    Arata Kawamura, Youji Iiguni, Yoshio Itoh

    págs. 855-861

    

  • Quantitative Evaluation of State-Preserbing Leakage Reduction Algorithm for L1 Data Caches

    Reiko Komiya

    págs. 862-868

    

  • Bitwidth Optimization for Low Power Digital FIR Filter Design

    Kosuke Tarumi

    págs. 869-875

    

  • Sub-operation Parallelism Optimization in SIMD Processor Core Synthesis

    Hideki Kawazu

    págs. 876-884

    

  • Performance Limitation of On-Chip Global Interconnects for High-Speed Signaling

    Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera

    págs. 885-891

    

  • Clock Period Minimization Method of Semi-Synchronous Circuits by Delay Insertion

    Yukihide Kohira, Atsushi Takahashi

    págs. 892-898

    

  • Architecture of IEEE802.11i Cipher Algorithms for Embedded Systems

    Yukio Mitsuyama

    págs. 899-906

    

  • An Integrated Approach of Variable Ordering and Logic Mapping into LUT-Array-Based PLD

    Tomonori Isumi

    págs. 907-914

    

  • Verifying Trace Equivalence of a Shared-Memory-Style Communication System

    Yoshinobu Kawabe, Ken Mano

    págs. 915-922

    

  • Iterative Parallel Genetic Algorithms Based on Biased Initial Population

    Morikazu Nakamura

    págs. 923-929

    

  • Constant Time Generation of Set Partitions

    Shin ichiro Kawano, Shin-ichi Nakano

    págs. 930-934

    

  • Fault-Tolerant Meshes with Constant Degree

    Toshinori Yamada

    págs. 935-940

    

  • Making Reactive Systems Highly Reliable by Hypersequential Programming

    Naoshi Uchihira

    págs. 941-947

    

  • IP Paging Schemes Adaptive to Mobile Host Parameters

    Hung Tuan Do, Yoshikuni Onozato

    págs. 948-953

    

  • A Linear Time Algorithm for Bi-Connectivity Augmentation of Graphs with Upper Bounds on Vertex-Degree Increase

    Takanori Fukuoka

    págs. 954-963

    

  • Siphon-Trap-Based Algorithms for Efficiently Computing Petri Net Invariants

    Akihiro Taguchi

    págs. 964-971

    

  • Adaptive Microphone Array System with Two-Stage Adaptation Mode Controller

    Yang Won Jung

    págs. 972-977

    

  • Equalizer-Aided Time Delay Tracking Based on L1-Normed Finite Differences

    Jonah Gamba, Tetsuya Shimamura

    págs. 978-987

    

  • Fixed-Lag Smoothing Algorithm under Non-independent Uncertainty

    Seiichi Nakamori, Aurora Hermoso Carazo, Josefa Linares Pérez

    págs. 988-995

    

  • A Low-Power. Small-Size 10-Bit Successive-Approximation ADC

    Mehdi Banihashemi, Khayrollah Hadidi, Abdollah Khoei

    págs. 996-1006

    

  • Globally Guaranteed Robustness Adaptive Fuzzy Control with Application on Highly Uncertain Robot Manipulators

    Chian Song Chiu

    págs. 1007-1014

    

  • Minimization of Reversible Wave Cascades

    Dimitris Voudouris, Stergios Stergiou, George Papakonstantinou

    págs. 1015-1023

    

  • Diagnosis of Timing Faults inScan Chains Using Single Excitation Patterns

    James Chien Mo Li

    págs. 1024-1030

    

  • A Low Latency Asynchronous FIFO Combining a Wave Pipeline With a Hanshake Scheme

    Jeong Gun Lee

    págs. 1031-1037