Hidetoshi Onodera

• Artículos de revistas (17)

• Artículos de revistas

  • Timing Analysis Considering Spatial Power/Ground Level Variation

    Masanori Hashimoto, J. Yamaguchi, Hidetoshi Onodera

    IEICE transactions on fundamentals of electronics, communications and computer, ISSN 0916-8508, Vol. 90, Nº 12, 2007, págs. 2661-2668

    

  • Manufacturability-Aware Design of Standard Cells

    H. Muta, Hidetoshi Onodera

    IEICE transactions on fundamentals of electronics, communications and computer, ISSN 0916-8508, Vol. 90, Nº 12, 2007, págs. 2682-2690

    

  • Interconnect RL Extraction Based on Transfer Characteristics of Transmission-Line

    Akira Tsuchiya, H. Hashimoto, Hidetoshi Onodera

    IEICE transactions on fundamentals of electronics, communications and computer, ISSN 0916-8508, Vol. 89, Nº 12, 2006, págs. 3585-3593

    

  • Statistical Analysis of Clock Skew Variation in H-Tree Structure

    Masanori Hashimoto, Tomonori Yamamoto, Hidetoshi Onodera

    IEICE transactions on fundamentals of electronics, communications and computer, ISSN 0916-8508, Vol. 88, Nº 12, 2005, págs. 3375-3381

    

  • Successive Pad Assignment for Minimizing Supply Voltage Drop

    Takashi Sato, Masanori Hashimoto, Hidetoshi Onodera

    IEICE transactions on fundamentals of electronics, communications and computer, ISSN 0916-8508, Vol. 88, Nº 12, 2005, págs. 3429-3436

    

  • Effects of On-Chip Inductance on Power Distribution Grid

    Atsushi Muramatsu, Masanori Hashimoto, Hidetoshi Onodera

    IEICE transactions on fundamentals of electronics, communications and computer, ISSN 0916-8508, Vol. 88, Nº 12, 2005, págs. 3564-3572

    

  • Performance Limitation of On-Chip Global Interconnects for High-Speed Signaling

    Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera

    IEICE transactions on fundamentals of electronics, communications and computer, ISSN 0916-8508, Vol. 88, Nº 4, 2005, págs. 885-891

    

  • Crosstalk Noise Optimization by Post-Layout Transistor Sizing

    Masanori Hashimoto, Hidetoshi Onodera

    IEICE transactions on fundamentals of electronics, communications and computer, ISSN 0916-8508, Vol. 87, Nº 12, 2004, págs. 3251-3257

    

  • INSTRUCTION-LEVEL POWER ESTIMATION METHOD BY CONSIDERING HAMMING DISTANCE OF REGISTERS

    Akihiko Higuchi, Kazutoshi Kobayashi, Hidetoshi Onodera

    IEICE transactions on fundamentals of electronics, communications and computer, ISSN 0916-8508, Vol. 87, Nº 4, 2004, págs. 823-829

    

  • Statistical Gate-Delay Modeling with Intra-Gate Variability

    Kenichi Okada, Kento Yamaoka, Hidetoshi Onodera

    IEICE transactions on fundamentals of electronics, communications and computer, ISSN 0916-8508, Vol. 86, Nº 12, 2003, págs. 2914-2922

    

  • Representative Frequency for Interconnect R(f)L(f)C Extraction

    Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera

    IEICE transactions on fundamentals of electronics, communications and computer, ISSN 0916-8508, Vol. 86, Nº 12, 2003, págs. 2942-2951

    

  • Crosstalk Noise Estimation for Generic RC Trees

    Masanori Hashimoto, Masao Takahashi, Hidetoshi Onodera

    IEICE transactions on fundamentals of electronics, communications and computer, ISSN 0916-8508, Vol. 86, Nº 12, 2003, págs. 2965-2973

    

  • Post-Layout Transistor Sizing for Power Reduction in Cell-Based Design

    Masanori Hashimoto, Hidetoshi Onodera

    IEICE transactions on fundamentals of electronics, communications and computer, ISSN 0916-8508, Vol. 84, Nº 11, 2001, págs. 2769-2777

    

  • A Dynamically Phase Adjusting PLL for Improvement of Lock-up Performance

    Takeo Yasuda, Hiroaki Fujita, Hidetoshi Onodera

    IEICE transactions on fundamentals of electronics, communications and computer, ISSN 0916-8508, Vol. 84, Nº 11, 2001, págs. 2793-2801

    

  • A real-time low-rate video compression algorithm using multi-stage hierarchical vector quantization

    Kazutoshi Kobayashi, Kazuhiko Terada, Hidetoshi Onodera

    IEICE transactions on fundamentals of electronics, communications and computer, ISSN 0916-8508, Vol. 82, Nº. 2, 1999, págs. 215-222

    

  • Lauout dependent matching analysis of CMOS circuits

    Kenichi Okada, Hidetoshi Onodera, Keikichi Tamaru

    IEICE transactions on fundamentals of electronics, communications and computer, ISSN 0916-8508, Vol. 82, Nº. 2, 1999, págs. 348-355

    

  • A power and delay optimization method using input reordering in cell-based CMOS circuits

    Masanori Hashimoto, Hidetoshi Onodera, Keikichi Tamaru

    IEICE transactions on fundamentals of electronics, communications and computer, ISSN 0916-8508, Vol. 82, Nº. 1, 1999, págs. 159-166

    

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