IEICE transactions on fundamentals of electronics, communications and computer

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  Año 2007, Vol. 90, Número 12

  • Chip-Level Substrate Coupling Analysis with Reference Structures for Verification

    Daisuke Kosaka

    págs. 2651-2660

    

  • Timing Analysis Considering Spatial Power/Ground Level Variation

    Masanori Hashimoto, J. Yamaguchi, Hidetoshi Onodera

    págs. 2661-2668

    

  • Closed-Form Expressions for Crosstalk Noise and Worst-Case Delay on Capacitively Coupled Distributed RC Lines

    H. Kawaguchi, D. D. Antono, T. Sakurai

    págs. 2669-2681

    

  • Manufacturability-Aware Design of Standard Cells

    H. Muta, Hidetoshi Onodera

    págs. 2682-2690

    

  • Look-Ahead Dynamic Threshold Voltage Control Scheme for Improving Write Margin of SOI-7T-SRAM

    M. Iijima

    págs. 2691-2694

    

  • Area Comparison between 6T and 8T SRAM Cells in Dual-Vdd Scheme and DVS Scheme

    Y. Morita

    págs. 2695-2702

    

  • An Efficient Diagnostic Scheme for RAMs with Simple Functional Faults

    J. Li, Cheng Sea Huang

    págs. 2703-2711

    

  • Transistor Sizing of LCD Driver Circuit for Technology Migration

    Masanori Hashimoto

    págs. 2712-2717

    

  • A Fast probability-Based Algorithm for Leakage Current Reduction Considering Controller Cost

    Tzung Han Wu, J. Tzeng

    págs. 2718-2726

    

  • Opposite-Phase Clock Tree for Peak Current Reduction

    Y. Nieh, Shi Yu Huang, S. Hsu

    págs. 2727-2735

    

  • Low Area Pipelined Circuits by the Replacement of Registers with Delay Elements

    B. Rosdi, Atsushi Takahashi

    págs. 2736-2742

    

  • A Relocation Method for Circuit Modifications

    K. Yanagibashi, Y. Takashima, Yuichi Nakamura

    págs. 2743-2751

    

  • Design Method for Numerical Function Generators Using Recursive Segmentation and EVBDDs

    Shinobu Nagayama, Tsutomu Sasao, J. Butler

    págs. 2752-2761

    

  • BDD Representation for Incompletely Specified Multiple-Output Logic Functions and Its Applications to the Design of LUT Cascades

    Munehiro Matsuura, Tsutomu Sasao

    págs. 2762-2769

    

  • Timing-Constrained Area Minimization Algorithm for Parallel Prefix Adders

    T. Matsunaga, Yusuke Matsunaga

    págs. 2770-2777

    

  • Satisfiability Checking for Logic with Equality and Uninterpreted Functions under Equicalence Constraints

    H. Kozawa, K. Hamaguchi, T. Kashiwabara

    págs. 2778-2789

    

  • Scheduling Methods for Asynchronous Circuits with Bundled-Data Implementations Based on the Approximation of Start Times

    Hiroshi Saito

    págs. 2790-2799

    

  • Generation of Pack Instruction Sequences for Media Processors Using Multi-Valued Decision Diagram

    Hatsukazu Tanaka

    págs. 2800-2809

    

  • Efficient Memory Utilization for High-Speed FPGA-Based Hardware Emulators with SDRAMs

    Kouhei Hosokawa, Katsunori Tanaka, Yuichi Nakamura

    págs. 2810-2817

    

  • High-Efficiency VLSI Architecture Design for Motion-Estimation in H.264/AVC

    C. C. Hsu, Mean Hom Ho

    págs. 2818-2825

    

  • An Approach to Solve Local Minimum Problem in Sound Source and Microphone Localization

    Kiyoshi Kobayashi

    págs. 2826-2834

    

  • A Distortion-Free Learning Algorithm for Feedforward Multi-Channel Blind Source Separation

    A. Horita, Kenji Nakayama, Akihiro Hirano

    págs. 2835-2845

    

  • An Algorithm to Improve the Performance of M-Channel Time-Interleaved A-D Converters

    K. Asami

    págs. 2846-2852

    

  • Function-Level Partitioning of Sequential Programs for Efficient Behavioral Synthesis

    Yoshitaka Hara

    págs. 2853-2862

    

  • "Adaptive Link Adjustment" Applied to the Fixed Charge Transportation Problem

    S. Soak

    págs. 2863-2876

    

  • Kalman-Filter Based Estimation of Electric Load Composition with Non-ideal Transformer Modeling

    S. Lee

    págs. 2877-2883

    

  • A Parallel Algorithm for NMNF Problems with a Large Number of Capacity Constraints

    Shieh Shing Lin

    págs. 2884-2890

    

  • Discrete Program-Size Dependent Software Reliability Assessment: Modeling, Estimation, and Goodness-of-Fit Comparisons

    S. Inoue, Shigeru Yamada

    págs. 2891-2902

    

  • The Vanstone-Zuccherato Schemes Revisited

    Naoki Kanayama, Shingenori Uchiyama

    págs. 2903-2907

    

  • Improved MACs from Differentially-Uniform Permutations

    K. Minematsu, Toshiyasu Matsushima

    págs. 2908-2915