IEICE transactions on fundamentals of electronics, communications and computer

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  Año 2006, Vol. 89, Número 12

  • Memory Size Computation for Real-Time Multimedia Applications Based on Polyhedral Decomposition

    Hongwei Zhu, Ilie I. Luican, Florin Balasa

    págs. 3378-3386

    

  • Synchronization Verification in System-Level Design with ILP Solvers

    Thanyapat Sakunkonchak, Satoshi Komatsu, Masahiro Fujita

    págs. 3387-3396

    

  • The AMS Extension to System Level Design Language - ApecC

    Yan Liu, Satoshi Komatsu, Masahiro Fujita

    págs. 3397-3407

    

  • Unified Representation for Speculative Scheduling: Generalized Condition Vector

    K. Wakabayashi

    págs. 3408-3415

    

  • An Efficient and Effective Algorithm for Online Task Placement with I/O Communications in Partially Reconfigurable FPGAs

    M. Tomono

    págs. 3416-3426

    

  • Bit-Length Optimization Method for High-Level Synthesis Based on Non-linear Programming Technique

    Nobuhiro Doi

    págs. 3427-3434

    

  • Multi-Clock Cycle Paths and Clock Scheduling for Reducing the Area of Pipelined Circuits

    B. Rosdi, Atsushi Takahashi

    págs. 3435-3442

    

  • Efficient Computation of Canonical Form under Variable Permutation and Negation for Boolean Matching in Large Libraries

    Debatosh Debnath, Tsutomu Sasao

    págs. 3443-3450

    

  • Coverage Estimation Using Transition Perturbation for Symbolic Model Checking in Hardware Verification

    X. Xu

    págs. 3451-3457

    

  • Hierarchical-Analysis-Based Fast Chip-Scale Power Estimation Method for Large and Complex LSIs

    Yuichi Nakamura, Takeshi Yoshimura

    págs. 3458-3463

    

  • Fast FPGA-Emulation-Based Simulation Environment for Custom Processors

    Yuichi Nakamura, Kouhei Hosokawa

    págs. 3464-3470

    

  • A PC-Based Logic Simulator Using a Look-Up Table Cascade Emulator

    Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura

    págs. 3471-3481

    

  • Delay Modeling and Critical-Path Delay Calculation for MTCMOS Circuits

    N. Ohkubo, Kimiyoshi Usami

    págs. 3482-3490

    

  • On-Chip Thermal Gradient Analysis Considering Interdependence between Leakage Power and Temperature

    Takahide Sato

    págs. 3491-3499

    

  • Formal Design of Arithmetic Circuits Based on Arithmetic Description Language

    N. Homma

    págs. 3500-3509

    

  • Compact Numerical Function Generators Based on Quadratic Approximation: Architecture and Synthesis Method

    Shinobu Nagayama, Tsutomu Sasao, J. Butler

    págs. 3510-3518

    

  • Design Method of High Performance and Low Power Functional Units Considering Delay Variations

    Kazuya Watanabe

    págs. 3519-3528

    

  • A Structural Approach for Transistor Circuit Synthesis

    H. Yoshida, Makoto Ikeda, Kunihiro Asada

    págs. 3529-3537

    

  • A Sampling Swith Design Procedure for Active Matrix Liquid Crystal Displays

    Satoshi Takahashi

    págs. 3538-3545

    

  • LSI Design Flow for Shot Reduction of Character Projection Electron Beam Direct Writing Using Combined Cell Stencil

    T. Kazama, Makoto Ikeda, Kunihiro Asada

    págs. 3546-3550

    

  • Routing of Monotonic Parallel and Orthogonal Netlists for Single-Layer Ball Grid Array Packages

    Y. Tomioka, Atsushi Takahashi

    págs. 3551-3559

    

  • Si-Substrate Modeling toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design

    Toshiki Kanamoto

    págs. 3560-3568

    

  • Simple Waveform Model of Inductive Interconnects by Delayed Quadratic Transfer Function with Application to Scaling Trend of Inductive Effects in VLSI's

    D. D. Antono

    págs. 3569-3578

    

  • Statistical Modeling of a Via Distribution for Yield Estimation

    T. Uezono, Kenichi Okada, K. Masu

    págs. 3579-3584

    

  • Interconnect RL Extraction Based on Transfer Characteristics of Transmission-Line

    Akira Tsuchiya, H. Hashimoto, Hidetoshi Onodera

    págs. 3585-3593

    

  • A VLSI Architecture for Variable Block Size Motion Estimation in H.264/AVC with Low Cost Memory Organization

    Yang Song

    págs. 3594-3601

    

  • Power-Efficient LDPC Decoder Architecture Based on Accelerated Message-Passing Schedule

    Kazunori Shimizu

    págs. 3602-3612

    

  • VLSI Implementation of a Modified Efficient SPIHT Encoder

    Win Hsien Huang, A. Su, Yao Ming Kuo

    págs. 3613-3622

    

  • A Sub-m W H.264 Baseline-Profile Motion Estimation Processor Core with a VLSI-Oriented Block Partitioning Strategy and SIMD/Systolic-Array Architecture

    J. Miyakoshi

    págs. 3623-3633

    

  • A 0.3-V Operating, Vth-Variation-Tolerant SRAM under DVS Environment for Memory-Rich SoC in 90-nm Technology Era and Beyond

    Y. Morita

    págs. 3634-3641