IEICE transactions on fundamentals of electronics, communications and computer

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  Año 2001, Vol. 84, Número 11

  • System-MSPA Design of H.263+ Video Encoder/Decoder LSI for Videotelephony Applications

    Chawalit Honsawek

    págs. 2614-2622

    

  • Design of High-Radix VLSI Dividers without Quotient Selection Tables

    Takafumi Aoki, Kimihiko Nakazawa, Tatsuo Higuchi

    págs. 2623-2631

    

  • Hierarchical Intellectual Property Protection Using Partially-Mergeable Cores

    Vikram Iyengar

    págs. 2632-2638

    

  • Area and Delay Estimation in Hardware/Software Cosynthesis for Digital Signal Processor Cores

    Nozomu Togawa

    págs. 2639-2647

    

  • An RTL Design-Space Exploration Method for High-Level Applications

    Peng Cheng Kao

    págs. 2648-2654

    

  • High-Level Synthesis of Pipelined Circuits from Modular Queue-Based Specifications

    Maria Cristina Marinescu, Martin Rinard

    págs. 2655-2664

    

  • Generalized Reasoning Scheme for Redundancy Addition and Removal

    José Alberto Espejo

    págs. 2665-2672

    

  • Timing Driven Gate Duplication in Technology Independent Phase

    Ankur Srivastava, Chunhong Chen, Majid Sarrafzadeh

    págs. 2673-2680

    

  • LUT-Array-Based PLD and Synthesis Approach Based on Sum of Generalized Complex Terms Expression

    Hiroshi Tsutsui

    págs. 2681-2689

    

  • A Routability Driven Technology Mapping Algorithm for LUT Based FPGA Designs

    Chi Chou Kao, Yen Tai Lai

    págs. 2690-2696

    

  • VLSI Floorplanning with Boundary Constraints Using Corner Block List Representation

    Yuchum Ma

    págs. 2697-2704

    

  • A Practical Clock Tree Synthesis for Semi-Synchronous Circuits

    Keiichi Kurokawa

    págs. 2705-2713

    

  • Reducing Wire Lengths in the Layout of Cyclic Shifters

    Peter Michael Seidel, Mark Hillebrand, Thomas Schürger

    págs. 2714-2721

    

  • Novel DFT Strategies Using Full/Partial Scan Designs and Test Point Insertion to Reduce Test Application Time

    Toshinori Hosokawa, Masayoshi Yoshimura, Mitsuyasu Ohta

    págs. 2722-2730

    

  • Optimization of Test Accesses with a Combined BIST and External Test Scheme

    Makoto Sugihara, Hiroto Yasuura

    págs. 2731-2738

    

  • Robust Performance Optimization Using Padding Nodes and Separator Sets

    Yutaka Tamiya

    págs. 2739-2745

    

  • An Algorithm for Statistical Static Timing Analysis Considering Correlations between Delays

    Shuji Tsukiyama, Masakazu Tanaka, Masahiro Fukui

    págs. 2746-2754

    

  • A System Level Optimization Technique for Application Specific Low Power Memories

    Tohru Ishihara, Kunihiro Asada

    págs. 2755-2761

    

  • Reducing Cache Energy Dissipation by Using Dual Voltage Supply

    Vasily G. Moshnyaga, Hiroshi Tsuji

    págs. 2762-2768

    

  • Post-Layout Transistor Sizing for Power Reduction in Cell-Based Design

    Masanori Hashimoto, Hidetoshi Onodera

    págs. 2769-2777

    

  • Analog Circuit Synthesis Based on Reuse of Topological Features of Prototype Circuits

    Hajime Shibata, Nobuo Fujii

    págs. 2778-2784

    

  • Using Non-slicing Topological Representations for Analog Placement

    Florin Balasa, Sarat C. Maruvada

    págs. 2785-2792

    

  • A Dynamically Phase Adjusting PLL for Improvement of Lock-up Performance

    Takeo Yasuda, Hiroaki Fujita, Hidetoshi Onodera

    págs. 2793-2801

    

  • A New Hardware/Software Partitioning Algorithm for DSP Processor Cores with Two Types of Register Files

    Nozomu Togawa

    págs. 2802-2807

    

  • Evolutionary Graph Generation System with Terminal-Color Constraint -An Application to Multiple-Valued Logic Circuit Synthesis-

    Masanori Natsui, Takafumi Aoki, Tatsuo Higuchi

    págs. 2808-2810

    

  • Enhancing Software Project Simulator toward Risk Prediction with Cost Estimation Capability

    Osamu Mizuno

    págs. 2812-2821

    

  • Weak Normality for Nonblocking Supervisor Control of Discrete Event Systems under Partial Observation

    Shigemasa Takai, Toshimitsu Ushio

    págs. 2822-2828

    

  • A Petri-Net-Based Model for the Mathematical Analysis of Multi-Agent Systems

    Kunihiko Hiraishi

    págs. 2829-2837

    

  • A Computation Method of LSN for Extended 2-b-SPGs

    Qi Wei Ge, Yasunori Sugimoto

    págs. 2838-2851

    

  • Performance Evaluation on Transient Time of Dynamic Workflow Changes

    Shingo Yanaguchi

    págs. 2852-2864