IEICE transactions on fundamentals of electronics, communications and computer

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  Año 2003, Vol. 86, Número 12

  • Statistical Gate-Delay Modeling with Intra-Gate Variability

    Kenichi Okada, Kento Yamaoka, Hidetoshi Onodera

    págs. 2914-2922

    

  • Parasitic Capacitance Modeling for Non-Planar Interconnects in Liquid Crystal Displays

    Sadahiro Tani

    págs. 2923-2932

    

  • Approximation Formula Approach for the Efficient Extraction of On-Chip Mutual Inductances

    Atsushi Kurokawa, Takashi Sato, Hiroo Masuda

    págs. 2933-2941

    

  • Representative Frequency for Interconnect R(f)L(f)C Extraction

    Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera

    págs. 2942-2951

    

  • Moment Computations of Lumped Coupled RLC Trees with Applications to Estimating Crosstalk Noise

    Herng Jer Lee, Chia Chi Chu, Wu Shiung Feng

    págs. 2952-2964

    

  • Crosstalk Noise Estimation for Generic RC Trees

    Masanori Hashimoto, Masao Takahashi, Hidetoshi Onodera

    págs. 2965-2973

    

  • A Design Methodology for Low EMI Noise LSI with Fast and Accurate Estimation

    Hiroyuki Tsujikawa, Shozo Hirano, Kenji Shimazaki

    págs. 2974-2982

    

  • Variable Pipeline Depth Processor for Energy Efficient Systems

    Akihiko Hyodo, Masanori Muroyama, Hiroto Yasuura

    págs. 2983-2990

    

  • A Low Power Embedded DRAM MAcro for Battery-Operated LSIs

    Takeshi Fujino

    págs. 2991-3000

    

  • Irredundant Low Power Address Bus Encoding Techniques Based on Adaptive Codebooks

    Satoshi Komatsu, Masahiro Fujita

    págs. 3001-3008

    

  • Counter Tree Diagrams: A Unified Framework for Analyzing Fast Addition Algorithms

    Jun Sakiyama

    págs. 3009-3019

    

  • Development of an IP Library of IEEE-754-Standard Single-Precision Floating-Point Dividers

    Hiroyuki Ochi

    págs. 3020-3027

    

  • Synthesis of Serial Local Clock Controllers for Asynchronous Circuit Design

    Nattha Sretasereekul

    págs. 3028-3037

    

  • Critical Path Selection for Deep Sub-Micron Delay Test and Timing Validation

    Jing Jia Liou

    págs. 3038-3048

    

  • DFT Timing Design Methodology for Logic BIST

    Yasuo Sato

    págs. 3049-3055

    

  • A Built-in Reseeding Technique for LFSR-Based Test Pattern Generation

    Youhua Shi

    págs. 3056-3062

    

  • Seed Selection Procedure for LFSR-Based Random Pattern Generators

    Kenichi Ichino

    págs. 3063-3071

    

  • A Method of Test Generation for Acyclic Sequential Circuits Using Single Stuck-at Fault Combinational ATPG

    Hideyuki Ichihara, Tomoo Inoue

    págs. 3072-3078

    

  • Implementation of Java Accelerator for High-Performance Embedded Systems

    Motoki Kimura

    págs. 3079-3088

    

  • Top-Down Retargetable Fraemwork with Token-Level Design for Accelerating Simulation Speed of Processor Architecture

    Jun Kyoung Kim, Ho Young Kim, Tag Gon Kim

    págs. 3089-3098

    

  • A Retargetable Simulator Generator for DSP Processor Cores with Packed SIMD-type Instructions

    Nozomu Togawa

    págs. 3099-3109

    

  • Efficient DDD-Based Interpretable Symbolic Characterization of Large Analog Circuits

    Sheldon X. D. Tan, C. J. Richard Shi

    págs. 3110-3118

    

  • A Fully Independently Adjustable, Integrable Simple Current Controlled Oscillator and Derivative PWM Signal Generator

    Montree Siripruchyanun, Paramonte Wardkein

    págs. 3119-3126

    

  • Red-Black Interval Trees in Device-Level Analog Placement

    Sarat C. Maruvada

    págs. 3127-3135

    

  • VLSI Module Placement with Pre-Placed Modules and with Consideration of Congestion Using Solution Space Smoothing

    Sheqin Dong

    págs. 3136-3147

    

  • An Improved Method of Convex Rectilinear Block Packing Based on Sequence-Pair

    Kazuya Wakata

    págs. 3148-3157

    

  • A Novel Timing-Driven Global Routing Algorithm Considering Coupling Effects for High Performance Circuit Design

    Jingyu Xu

    págs. 3158-3167

    

  • Compact Representations of Logic Functions Using Heteroneneous MDDs

    Shinobu Nagayama, Tsutomu Sasao

    págs. 3168-3175

    

  • Multi-Cycle Path Detection for Sequential Circuits and Its Application to Real Designs

    Hiroyuki Higuchi

    págs. 3176-3183

    

  • Bit Length Optimization of Fractional Part on Floating to Fixed Point Conversion for High-Level Synthesis

    Nobuhiro Doi

    págs. 3184-3191