IEICE transactions on fundamentals of electronics, communications and computer

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  Año 1999, Vol. 82, Número 2

  • Low-power architectures for programmable multimedia processors

    Takao Nishitani

    págs. 184-196

    

  • System electronics technologies for video processing and applications

    Tomio Kishimoto, Hironori Yamauchi, Ryota Kasai

    págs. 197-205

    

  • Media core processor for multimedia application sysem

    Kosuke Yoshioka, Makooto Hirai, Kozo Kimura

    págs. 206-214

    

  • A real-time low-rate video compression algorithm using multi-stage hierarchical vector quantization

    Kazutoshi Kobayashi, Kazuhiko Terada, Hidetoshi Onodera

    págs. 215-222

    

  • A pipelined architecture for nonmalized LMS adaptive digital filters

    Akio Harada, Kiyoshi Nishikawa, Hitoshi Kiya

    págs. 223-229

    

  • A transformation method of a CORDIC ARMA lattice filter for signal sybthesis

    Shin'ichi Shiraishi, Miki Haseyama, Hideo Kitajima

    págs. 230-237

    

  • Performance enhancement on digital signal processors with complex arithmetic capability

    Yoshimasa Negishi, Eiji Watanabe, Akinori Nishihara

    págs. 238-245

    

  • A method for circular pattern recognition in a binary image and its implementation onto an FPGA

    Yusuke Tokunaga, Takahiro Inoue

    págs. 246-253

    

  • Design of fully balanced analog systems based on ordinary and/or modified single-ended opamps

    Zdzislaw Czarnul, Tetsuro Itakura, Noriaki Dobashi

    págs. 256-270

    

  • Substrate noise simulation techniques for analor-digital mixed LSI design

    Makoto Nagata, Atsushi Iwata

    págs. 271-278

    

  • A 10 bit current-mode CMOS A/D converter with a current predictor and a modular current reference

    Soung Hoon Shim, Kwang Sub Yoon

    págs. 279-285

    

  • A 1.5 V, 8m W, 8 b, 15 Msps BiCMOS A/D converter

    Michio Yotsuyanagi, Hiroshi Hasegawa, Masaharu Satoh

    págs. 286-292

    

  • Low-power area-efficient pipelined A/D converter design using a single-ended amplifier

    Daisuke Miyazaki, Shoji Kawahito, Yoshiaki Tadokoro

    págs. 293-300

    

  • Differential analog data path DC offset calibration methods

    Takeo Yasuda, Hajime Andoh

    págs. 301-306

    

  • A CMOS offset phase locked loop for a GSM transmitter

    Taizo Yamawaki, Masaru Kokubo, Hiroshi Hagisawa

    págs. 307-312

    

  • A 1.9-GHz direct conversion trasmitter IC with low power on-chip frequency doubler

    Shoji Otaka, Ryuichi Fujimoto, Hiroshi Tanimoto

    págs. 313-319

    

  • GaAs FEt current-mode integrators and their application to filters

    Nobukazu Takai, Nobuo Fujii

    págs. 320-326

    

  • A CMOS analog multiplier free from mobility reduction and body effect

    Eitake Ibaragi, Akira Hyogo, Keitaro Sekine

    págs. 327-334

    

  • Multi-input floating gate differential amplifier and applications to intelligent sensors

    Takeyasu Sakai, Hiromasa Nagai, Takashi Matsumoto

    págs. 335-340

    

  • A fast and accurete method of redesigning analog subcircuits for technology scaling

    Seiji Funaba, Akihiro Kitagawa, Toshiro Tsukada

    págs. 341-347

    

  • Lauout dependent matching analysis of CMOS circuits

    Kenichi Okada, Hidetoshi Onodera, Keikichi Tamaru

    págs. 348-355

    

  • An analog-digital merged neural circuit using pulse width modulation technique

    Takashi Morie, Jun Funakoshi, Makoto Nagata

    págs. 356-363

    

  • Integrated circuits of map chaos generators

    Hidetoshi Tanaka, Shigeo Saito, Koji Nakajima

    págs. 364-369

    

  • A content-addressable memory using "switched diffusion analog memory with feedback circuit"

    Tomochika Harada, Shigeo Sato, Koji Nakajima

    págs. 370-377

    

  • Low voltage high-speed CMOS square-low composite transistor cell

    Changku Hwang, Akira Hyogo, Hong Sun Kim

    págs. 378-379

    

  • A simple pole-assignment scheme for designing multivariable self-tuning controllers

    Toru Yamamoto, Yujiro Inouye, Masahiro Kaneda

    págs. 380-389

    

  • Construct message authentication code with one-way hash function and block ciphers

    Yi Shiung Yeh, Chan Chi Wang

    págs. 390-393

    

  • The complexity of an optimal file transfer problem

    Yoshihiro Kaneko, Shoji Shinoda

    págs. 394-397

    

  • Adaptive simulated annealing in CNN template learning

    Brett Chandler, Csaba Rekeczky, Yoshifumi Nishio

    págs. 398-402

    

  • Two-level quantizer design using genetic algorithm

    Wen Jan Chen, Shen-Chuan Tai, Po Jen Cheng

    págs. 403-406