IEICE transactions on fundamentals of electronics, communications and computer

• 

  Año 2005, Vol. 88, Número 12

  • Adaptive Mode Control for Low-Power Cahces Based on Way-Prediction Accuracy

    Hidekazu Tanaka, Koji Inoue

    págs. 3274-3281

    

  • Low Power and Fault Tolerant Encoding Methods for On-Chip Data Transfer in Practical Applications

    Satoshi Komatsu, Masahiro Fujita

    págs. 3282-3289

    

  • Power-Minimum Frequency/Voltage Cooperative Management Method for VLSI Processor in Leakage-Dominant Technology Era

    Kentaro Kawakami

    págs. 3290-3297

    

  • Low-Power Field-Programmable VLSI Using Multiple Supply Voltages

    Weisheng Chong, Masanori Hariyama, Michitaka Kameyama

    págs. 3298-3305

    

  • Trace-Driven Performance Simulation Modeling for Fast Evaluatiion of Multimedia Processor by Simulation Reuse

    Ho Young Kim, Tag Gon Kim

    págs. 3306-3314

    

  • An Equivalence Cheking Method for C Descriptions Based on Symbolic Simulation with Textual Differences

    Takeshi Matsumoto, Hiroshi Saito, Masahiro Fujita

    págs. 3315-3323

    

  • Logic Synthesis Technique for High Speed Differential Dynamic Logic with Asymmetric Slope Transition

    Masao Morimoto

    págs. 3324-3331

    

  • Exact Minimization of FPRMs for Incompletely Specified Functions by Using MITBDDs

    Debatosh Debnath, Tsutomu Sasao

    págs. 3332-3341

    

  • A Desing Algorithm for Sequential Circuits Using LUT Rings

    Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura

    págs. 3342-3350

    

  • An Engineering Change Orders Design Method Based on Patchwork-Like Partitioning for High

    Yuichi Nakamura, Ko Yoshikawa, Takeshi Yoshimura

    págs. 3351-3357

    

  • Circuit Performance Prediction Considering Core Utilization with Interconnect Length Distribution Model

    Hidenari Nakashima

    págs. 3358-3366

    

  • Modeling the Effective Capacitance of Interconnect Loads for Predicting CMOS Gate Slew

    Zhangcai Huang

    págs. 3367-3374

    

  • Statistical Analysis of Clock Skew Variation in H-Tree Structure

    Masanori Hashimoto, Tomonori Yamamoto, Hidetoshi Onodera

    págs. 3375-3381

    

  • On-Chip Thermal Gradient Analysis and Temperature Flattening for SoC Desing

    Takashi Sato

    págs. 3382-3389

    

  • A Graph Based Soft Module Handling in Floorplan

    Hiroaki Itoga, Chikaaki Kodama, Kunihiro Fujiyoshi

    págs. 3390-3397

    

  • An Incremental Placement Algorithm for Building Block Layout Desing Based on the O-Tree Representation

    Jing Li, Juebang Yu, Hiroshi Miyashita

    págs. 3398-3404

    

  • Navigating Register Placement for Low Power Clock Network Desing

    Yongqiang Lu

    págs. 3405-3411

    

  • Efficient Large Scale Integration Power/Ground Network Optimization Based on Grid Genetic Algorithm

    Yun Yang

    págs. 3412-3420

    

  • Power-Supply Noise Reduction with Design for Manufacturability

    Hiroyuki Tsujikawa

    págs. 3421-3428

    

  • Successive Pad Assignment for Minimizing Supply Voltage Drop

    Takashi Sato, Masanori Hashimoto, Hidetoshi Onodera

    págs. 3429-3436

    

  • Evaluation of X Architecture Using Interconnect Length Distribution

    Hidenari Nakashima

    págs. 3437-3444

    

  • Wire Length Distribution Model for System LSI

    Takanori Kyogoku

    págs. 3445-3452

    

  • Second-Order Polynomial Expressions for On-Chip Interconnect Capacitance

    Atsushi Kurokawa

    págs. 3453-3462

    

  • A Method of Precise Estimation of Physical Parameters in LSI Interconnect Structures

    Toshiki Kanamoto

    págs. 3463-3470

    

  • Efficient Dummy Filing Methods to Reduce Interconnect Capacitance and Number of Dummy Metal Fills

    Atsushi Kurokawa

    págs. 3471-3478

    

  • On the Computational Synthesis of CMOS Voltage Followers

    Esteban Tlelo Cuautle, Delia Torres Muñoz, Leticia Torres Papaqui

    págs. 3479-3484

    

  • Exact Minimum-Width Transistor Placement for Dual and Non-dual CMOS Cells

    Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada

    págs. 3485-3491

    

  • A 95 mW MPEG2 MP@HL Motion Estimation Processor Core for Portable High-Resolution Video Application

    Yuichiro Murachi

    págs. 3492-3499

    

  • Quality and Power Efficient Architecture for the Discrete Cosine Transform

    Chi Chia Sung

    págs. 3500-3507

    

  • VLSI Implementation of Lifting Wavelet Transform of JPEG2000 with Efficient RPA (Recursive Pyramid Algorithm) Realization

    Gab Cheon Jung, Seong Mo Park

    págs. 3508-3515