Nesting of reducible and irreducible loops
Paul Havlak
págs. 557-567
Interprocedural control flow analysis of first-order programs with tail-call optimization
Saumya K. Debray, Todd A. Proebsting
págs. 568-585
A refinement calculus for the synthesis of verified hardware descriptions in VHDL
Peter T. Breuer, Carlos Delgado Kloos
págs. 586-616
págs. 617-638
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