pág. 95
An Interconnect Scaling Scheme with Constant On-Chip Inductive Effects
Kaustav Banerjee, Amit Mehrotra
págs. 97-105
An Accurate Transient Analysis of High-Speed Package Interconnects Using Convolution Technique
Wendemagegnehu T. Beyene, Chuck Yuan
págs. 107-120
Integrated Inductors Modeling for Library Development and Layout Generation
Javier del Pino, Benito González, José R. Sendra, Javier García, Antonio Hernández
págs. 121-132
Cross-Coupled Noise Propagation in VLSI Designs
David Blaauw, Chanhee Oh, Vladimir Zolotov, Rajendran Panda
págs. 133-142
Closed-Form Crosstalk Noise Delay Metrics
Malgorzata Marek-Sadowska, Lauren Hui Chen
págs. 143-156
Design of Digital Window Comparators and their Implementation within Mixed-Signal DfT Schemes
M. J. Ohletz, Daniela De Venuto, Bruno Riccò
págs. 157-168
Automated System-Level Test Development for Mixed-Signal Circuits
Alex Orailoglu, Sule Ozev
págs. 169-178
Comparator Generation and Selection for Highly Linear CMOS Flash Analog-to-Digital Converter
Kyusun Choi, Jincheol Yoo, Daegyu Lee
págs. 179-187
Mandeep Singh, Israel Koren
págs. 189-197
Layout-Specific Circuit Evaluation in 3-D Integrated Circuits
Syed M. Alam, Donald E. Troxel, Carl V. Thompson
págs. 199-206
págs. 207-214
Interconnect Geometry Optimization Using Modular Artificial Neural Networks
V. Venkatraman, A. Ilumoka, B. Kalla
págs. 215-225
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