Lifetime-aware scheduling in high level synthesis

• Autores: Siavash Es'haghi, Mohammad Eshghi
• Localización: Microelectronics reliability, ISSN 0026-2714, Nº. 91-1, 2018, págs. 86-97
• Idioma: inglés
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• Resumen

  • Among various reliability challenges, accelerated aging is of particular importance. The flexibility of high-level synthesis (HLS) can be employed at an affordable cost to increase the reliability, and in particular lifetime, of the systems. In this paper, we extract the aging characteristics of the functional units (FUs), then, a scheduling method based on integer linear programming (ILP) is proposed to increase the lifetime, using the aging characteristics of the FUs. The proposed method extends the lifetime beyond the minimum expected value, with the minimum latency overhead, by applying the operation chaining and multicycling techniques in an aging-aware approach. The constraint matrix of the proposed ILP formulation is totally unimodular. This technique is suitable for both data-flow intensive and control-flow intensive designs and is applicable for large circuits. Experimental results show that the proposed approach increases the lifetime by 2.33×, and increases the latency by an average of 19.8%.