A versatile framework for the statistical characterization of cmos time-zero and time-dependent variability with array-based ics
- Autores: Javier Diaz Fortuny
- Directores de la Tesis: Javier Martín Martínez (dir. tes.), Rosana Rodríguez Martínez (dir. tes.)
- Lectura: En la Universitat Autònoma de Barcelona ( España ) en 2019
- Idioma: español
- Tribunal Calificador de la Tesis: Francesc Moll Echeto (presid.), Esteve Amat Bertran (secret.), Florian Cacho (voc.)
- Programa de doctorado: Programa de Doctorado en Ingeniería Electrónica y de Telecomunicación por la Universidad Autónoma de Barcelona
- Materias:
- Enlaces
- Tesis en acceso abierto en: TESEO
- Resumen
Since the invention in 1960 of the Metal Oxide Semiconductor Field Effect Transistor (MOSFET), the CMOS semiconductor industry has invariably invented new feats to progressively reduce the minimum gate length, from the micrometer scale (< 10-μm) to the nowadays 7-14-nm gate lengths or the new 5-nm technology node predicted to be manufactured in 2020-2021, all with the aim of fabricating more reliable devices and even more advanced circuits and systems, with billions of transistors per chip.
With all the benefits that transistor size scaling brings to power, area and performance, approaching the atomic scale poses an important peril: the increase of variations of the transistor’s intrinsic performance, thus critically compromising the fundamental reliability of the fabricated devices and circuits. In this way, variations of fabricated transistor parameters, like for instance threshold voltage or mobility, as well as their degradation during circuit functionality, have become an increasing concern in nanometer integrated circuit design. Moreover, a significant increase of gate leakage current has emerged due to the scaling in the thickness of the transistor’s insulator. In this scenario, to increase performance and reliability of the fabricated devices, new and more complex stack materials have been introduced, such as Silicon oxynitride (SiON), High-K Metal gate insulators (HKMG) and new devices geometries like FinFETs, FDSOI or MuGFETs have emerged in ultra-scaled technology nodes to continue with the scaling trend and have better control of the short channel effects.
The variability in the transistor parameters, stochastic by nature, must be massively characterized to capture those variations with a representative and sound statistical sampling. Variability sources are divided in two different types: first, the time-zero variability, typically known as process variability which occurs during the fabrication process and consists in a permanent either random or systematic, shift of the device parameters; second, the time-dependent variability, which occurs during device or circuit operation over time and includes transient effects like Random Telegraph Noise, and degradation mechanisms or aging effects, like Hot Carrier Injection, Bias Temperature Instability, Time Dependent Dielectric Breakdown, Stress Induced Leakage Current, etc., which are potential sources of device and IC variability that can lead transistors to a progressive degradation or to a permanent failure.
To reduce or mitigate variability effects, novel variability-aware circuit design techniques are required to assess the combined impact of time-zero and time-dependent variability in advanced technology nodes. Variability-aware techniques utilize accurate compact models, which are based in statistical characterization of individual MOSFET devices. In this regard, providing statistically accurate characterization of TZV and TDV effects in modern CMOS technologies has, therefore, become a key step in the path towards attaining truly reliable integrated circuits. In this context, this thesis will contribute to the characterization and lifetime prediction of nanometer CMOS technologies through a thorough study of an extensive statistical data samples. To do so, issues related to typical serial characterization techniques, which require months or even years of continuous non-stop device testing, are overcome thanks to a novel and versatile array-based IC chip design in conjunction with a full-custom characterization framework. These two key elements, the IC and the framework, can effectively be utilized to statistically characterize the impact of different device variability sources in nanometer-scale MOSFETs while significantly and outstandingly reducing the required characterization time.
