Contribución al estudio de las interferencias electromagnéticas conducidas en circuitos integrados

• Autores: Néstor Berbel Artal
• Directores de la Tesis: Ignacio Gil Galí (dir. tes.), Raúl Fernández García (dir. tes.)
• Lectura: En la Universitat Politècnica de Catalunya (UPC) ( España ) en 2015
• Idioma: español
• Tribunal Calificador de la Tesis: Enrique Alberto Miranda (presid.), Javier Gago Barrio (secret.), Javier Jose Sieiro Cordoba (voc.)
• Materias:
  • Ciencias tecnológicas
    • Tecnología electrónica
• Enlaces
  • Tesis en acceso abierto en: TDX
• Resumen

  • This thesis is focused on the conducted electromagnetic Interference generated at Integrated Circuit (IC) Level. Recently, several electrical models have been proposed in order to describe EMI at IC level, but they have several limitations. The first drawback is that these electrical models do not take into account the wear-out mechanisms on the EMI behaviour. The wear-out mechanisms are due to the dielectric degradation when an electric stress is applied to the oxide gate. Due to this degradation, the MOSFET characteristics are shifted. Therefore, the evaluation of wear-out mechanisms allow the designers, during the IC design, to predict the circuit behaviour along its lifetime. However, the impact of these wear-out mechanisms on the conducted EMI drift at IC level has not been deeply investigated. Hence, one of the aims of this thesis will be focused on the impact of wear-out mechanisms in signal integrity and conducted EMI at IC level. Moreover, current integrated circuits have a high operation frequency. Thus, the electromagnetic noise induced on those devices presents a higher harmonic content. For this reason, the electronics industry requires electrical models to predict high frequency conducted emissions. In this sense, the other aim of this thesis will be focused on expanding the current EMI models beyond 1 GHz. The IC behaviour may be affected by temperature, as well as conducted emission levels. Therefore, the proposed electrical model will take into account the impact of temperature. The experimental results have been obtained with three integrated circuits, two of them are specific test chip designed by Freescale Semiconductor, Inc., and the third IC is a commercial circuit of Maxim Integrated Circuits. This document is structured in four chapters. Chapter 1 describes the main wear-out mechanisms and the electromagnetic compatibility at IC level. The different EMI produced at IC are explained. Also, it describes aging methods to characterize the impact of wear-out mechanisms on MOS devices. Furthermore, the EMI characterization methods are explained and different EMC electrical models are described. To confirm the accuracy of the EMC models, the ¿Feature Selective Validation¿ (FSV) technique has been used. On this chapter, the FSV method and its application on computational electromagnetism is detailed. The chapter ends with the state of the art on wear-out mechanisms and EMI at IC level. Chapter 2 analyzes the IC reliability. The IC aging of the MOSFET I-V curve characteristics is studied, for further EMI characterization of the impact of wear-out mechanisms. The experimental results are presented at the end of Chapter 2. Chapter 3 presents an electrical model to characterize the conducted emissions of an IC up to 3 GHz. This electrical model considers the impact of temperature. The proposed model is validated with experimental results and verified with the FSV method. Chapter 4 summarizes the conclusions of the thesis and the main contributions. In addition, a list of the publications derived from this thesis is included. Finally, the chapter presents the lines for future research.