Journal of electronic testing: Theory and applications

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  Año 2004, Número 2

  • A Design for Testability Scheme for CMOS LC-Tank Voltage Controlled Oscillators

    L. Dermentzoglou

    págs. 133-142

    

  • Analog Switches in Programmable Analog Devices Quiescent Defective Behaviours

    R. Rodriguez Montanes

    págs. 143-153

    

  • A Low-Cost At-Speed BIST Architecture for Embedded Processor and SRAM Cores

    M. H. Tehranipour

    págs. 155-168

    

  • Testability Trade-Offs for BIST Data Paths

    B. M. Al Hashimi, N. Nicolici

    págs. 169-179

    

  • Scalable Delay Fault BIST for Use with Low-Cost ATE

    I. Polian, B. Becker

    págs. 181-197

    

  • Analysis of Test Application Time for Test Data Compression Methods Based on Compression Codes

    A. Chandra, Krishnendu Chakrabarty

    págs. 199-212

    

  • Scan Latch Design for Test Applications

    A. M. Sheth

    págs. 213-216