The threshold voltage degradation model of N Channel VDMOSFETs under PBT stress

• Autores: Xuerong Ye, Kaixin Zhang, Cen Chen, Zhongwei Li, Yue Wang, Guofu Zhai
• Localización: Microelectronics reliability, ISSN 0026-2714, Nº. 91-1, 2018, págs. 46-51
• Idioma: inglés
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• Resumen

  • With the voltage increasing in DC power systems, positive bias temperature instability (PBTI) induced gate oxide degradation of commercial n-channel power vertical double diffused MOSFETs (VDMOSFETs) has been greatly enhanced recently. However, it is not mature in some aspects, e.g., parametric models of PBTI and the turn-around phenomenon are rarely studied. Aiming at these disadvantages, the experimental study and the argument are proposed in this paper. First, the simulation was used to identify and verify the threshold voltage as the characteristic parameter and the accelerated experiment test was conducted to collect data for degradation modeling. Then, a Power law-Arrhenius combined model was adopted in the degradation model to take into account the electrical and thermal influence. Besides that, a two-phase PBTI degradation model was presented, which can describe the turn-around phenomenon. Moreover, the comparison of the estimated remaining useful life (RUL) results with the experimental data verified the accuracy of the developed model.