Atmospheric neutron single event effect test on Xilinx 28 nm system on chip at CSNS-BL09

• Autores: Weitao Yang, Yonghong Li, Yang Li, Zhiliang Hu, Fei Xie, Chaohui He, Songlin Wang, Bin Zhou, Huan He, Waseem A. Khan, Tianjiao Liang
• Localización: Microelectronics reliability, ISSN 0026-2714, Nº. 99, 2019, págs. 119-124
• Idioma: inglés
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• Resumen

  • China Spallation Neutron Source (CSNS)–Beam Line 09 (BL09) was used to study 28 nm system on chip (SoC) atmospheric neutron single event effect for the first time. The on chip memory (OCM), D-Cache and BRAM blocks were tested respectively. Different single event effects were detected, such as single bit upset, multi cell upset and single event functional interruption. The experiment illustrated that there is a significant discrepancy in results whether neutron from 1 MeV to 10 MeV contributions are considered in studying 28 nm SoC single event effect. The experiment and Geant4 simulation results indicated that the influence of 1 MeV to 10 MeV neutron cannot be neglected. The average bit cross section and soft error rate (SER) per Mbit at Beijing sea level of the 28 nm SoC are 1.50 × 10−15 cm2·bit−1 and 22 FIT·Mbit−1.