Journal of electronic testing: Theory and applications

• 

  Año 2005, Número 5

  • Editorial

    V. D. Agrawal

    pág. 459

    

  • The Newsletter of Test Technology Council of the IEEE Computer Society

    B. C. Kim

    págs. 461-462

    

  • Defect Detection Using Quiescent Signal Analysis

    C. Patel, J. Plusquellic, A. Singh

    págs. 463-483

    

  • Incremental Design Debugging in a Logic Synthesis Environment

    A. Veneris, J. B. Liu

    págs. 485-494

    

  • Functional Fault Equivalence and Diagnostic Test Generation in Combinational Logic Circuits Using Conventional ATPG

    A. Veneris

    págs. 495-502

    

  • A Formal Approach to On-Line Monitoring of Digital VLSI Circuits: Theory, Design and Implementation

    S. Biswas, S. Mukhopadhyay

    págs. 503-537

    

  • Concurrent Error Detection in a Bit-Parallel Systolic Multiplier for Dual Basis of GF(2m)

    Chiou-Yng Lee, Che Wun Chiou

    págs. 539-549

    

  • Efficient March Test Procedure for Dynamic Read Destructive Fault Detection in SRAM Memories

    Serge Pravossoudovitch, L. Dilillo, Patrick Girard

    págs. 551-561