IEICE transactions on electronics

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  Año 2006, Vol. 89, Número 11

  • Solid-Electrolyte Nanometer Switch (INVITED)

    H. Kawaura, S. Kaeriyama, M. Mizuno, K. Terabe, T. Hasegawa, M. Aono, N. Banno, T. Sakamoto, N. Iguchi

    págs. 1492-1498

    

  • Carbon Nanotube Technologies for LSI via Interconnects (INVITED)

    Y. Awano

    págs. 1499-1503

    

  • Single-Electron Logic Systems Based on a Graphical Representation of Digital Functions (INVITED)

    Y. Amemiya

    págs. 1504-1511

    

  • Design and Evaluation of a Massively Parallel Processor Based on Matrix Architecture (INVITED)

    T. Shimizu, M. Nakajima

    págs. 1512-1518

    

  • An On-Chip Supply-Voltage Control System Considering PVT Variations for Worst-Caseless Lower Voltage SoC Design

    M. Okamoto, H. Noda, K. Dosaka, K. Arimoto, T. Gyohten, F. Morishita, I. Hayashi

    págs. 1519-1825

    

  • A Differential Cell Terminal Biasing Scheme Enabling a Stable Write Operation against a Large Random Threshold Voltage (V~t~h) Variation

    H. Yamauchi, T. Suzuki, Y. Yamagami

    págs. 1526-1534

    

  • An Integrated Timing and Dynamic Supply Noise Verification for Multi-10-Million Gate SoC Designs

    S. Miyahara, M. Hirata, K. Satoh, H. Tsujikawa, K. Shimazaki, M. Nagata, M. Fukazawa

    págs. 1535-1543

    

  • Chip-Level Performance Improvement Using Triple Damascene Wiring Design Concept for the 0.13 mum CMOS Generation and Beyond

    K. Takeda, T. Tanaka, T. Takewaki, N. Oda, H. Kunishima, T. Kyouno

    págs. 1544-1550

    

  • Minimizing Energy Consumption Based on Dual-Supply-Voltage Assignment and Interconnection Simplification

    M. Hariyama, S. Yamadera, M. Kameyama

    págs. 1551-1558

    

  • Measurement-Based Analysis of Delay Variation Induced by Dynamic Power Supply Noise

    M. Fukazawa

    págs. 1559-1566

    

  • High-Frequency Low-Noise Voltage-Controlled LC-Tank Oscillators Using a Tunable Inductor Technique

    C. Y. Yang, M. T. Tsai

    págs. 1567-1574

    

  • Design and Evaluation of a NULL-Convention Circuit Based on Dual-Rail Current-Mode Differential Logic

    N. Onizawa

    págs. 1575-1580

    

  • Back-End Design of a Collision-Resistive RFID System through High-Level Modeling Approach

    Y. Fukumizu, M. Nagata, K. Taki

    págs. 1581-1590

    

  • Design of a Low-Power Quaternary Flip-Flop Based on Dynamic Differential Logic

    A. Mochizuki, H. Shirahama

    págs. 1591-1597

    

  • Implementation of a High-Speed Asynchronous Data-Transfer Chip Based on Multiple-Valued Current-Signal Multiplexing

    T. Takahashi

    págs. 1598-1604

    

  • Vision Chip Architecture for Detecting Line of Sight Including Saccade

    M. Toda, Takayuki Kawashima, J. Akita, H. Takagi, T. Nagasaki

    págs. 1605-1611

    

  • A Reliability-Enhanced TCAM Architecture with Associated Embedded DRAM and ECC

    T. Koide, F. Morishita, H. Noda, K. Dosaka, H. J. Mattausch

    págs. 1612-1619

    

  • Cache-Based Network Processor Architecture: Evaluation with Real Network Traffic

    M. Okuno, S. Nishimura, S. I. Ishida

    págs. 1620-1628

    

  • A Power- and Area-Efficient SRAM Core Architecture with Segmentation-Free and Horizontal/Vertical Accessibility for Super-Parallel Video Processing

    H. Kawaguchi, M. Yoshimoto, J. Miyakoshi, Y. Murachi, T. Ishihara

    págs. 1629-1636

    

  • A VLSI Spiking Feedback Neural Network with Negative Thresholding and Its Application to Associative Memory

    K. Sasaki, T. Morie, A. Iwata

    págs. 1637-1644

    

  • Systematic Interpretation of Redundant Arithmetic Adders in Binary and Multiple-Valued Logic

    N. Homma, T. Aoki, T. Higuchi

    págs. 1645-1654

    

  • A Multi-Context FPGA Using Floating-Gate-MOS Functional Pass-Gates

    M. Hariyama, S. Ogata, M. Kameyama

    págs. 1655-1661

    

  • CMOS Image Sensor Using Negative-Feedback Resetting to Obtain Variably Smoothed Images

    M. Ikebe, K. Saito

    págs. 1662-1669

    

  • A Low-Power Write Driver for Hard Disk Drives

    F. Yuki, T. Kawashimo, H. Yamashita, M. Yagyu

    págs. 1670-1673

    

  • A Cost Effective Interconnection Network for Reconfigurable Computing Processor in Digital Signal Processing Applications

    C. W. Chiu, Y. K. Lai, L. F. Chen, J. C. Chen

    págs. 1674-1675

    

  • Error Analysis of the Multilevel Fast Multipole Algorithm

    S. Ohnuki, W. C. Chew

    págs. 1676-1681

    

  • Spread-Spectrum Clock Generator for Serial ATA with Multi-Bit SigmaDelta Modulator-Controlled Fractional PLL

    T. Noto, M. Suzuki, S. Suzuki, T. Hayasaka, T. Takahashi, M. Kokubo, T. Kawamoto, T. Oshima

    págs. 1682-1687

    

  • Autonomous di/dt Control of Power Supply for Margin Aware Operation

    T. Nakura, M. Ikeda, K. Asada

    págs. 1689-1694

    

  • Calculation of Measurement Uncertainties of Synchronously Sampled AC Signals in Nonideal Synchronization with Fundamental Frequency

    P. Petrovic

    págs. 1695-1699

    

  • Wave Absorber Formed by Arranging Cylindrical Bars at Intervals for Installing between ETC Lanes

    T. Aoyagi, Osamu Hashimoto, K. Matsumoto, T. Ozawa, T. Nakamura

    págs. 1700-1703