IEICE transactions on fundamentals of electronics, communications and computer

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  Año 1999, Vol. 82, Número 11

  • Improving dictionary-based code compression in VLIW architectures

    Sang-Joon Nam, In Cheol Park, Chong Min Kyung

    págs. 2318-2324

    

  • A hardware/software cosynthesis system for digital signal processor cores

    Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

    págs. 2325-2337

    

  • Hardware synthesis from C programs with estimation of bit length of variables

    Osamu Ogawa, Kazuyoshi Takagi, Yasufumi Itoh

    págs. 2338-2346

    

  • High-level synthesis with SDRAMs and RAMBUS DRAMs

    Asheesh Khare, Preeti R. Panda, Nikil Dutt

    págs. 2347-2355

    

  • A performance optimization method for pipelined ASPs in consideration of clock frequency

    Katsuya Shinohara, Norimasa Ohtsuki, Yoshinori Takeuchi

    págs. 2356-2365

    

  • A memory power optimization technique for application specific embedded systems

    Tohru Ishihara, Hiroto Yasuura

    págs. 2366-2374

    

  • Performance evaluation of STRON: a hardware implementation of a real-time OS

    Takumi Nakano, Yoshiki Komatsudaira, Akichika Shiomi

    págs. 2375-2382

    

  • Clock period minimization of semi-synchronous circuits by gate-level delay insertion

    Tomoyuki Yoda, Atsushi Takahashi

    págs. 2383-2389

    

  • Logic minimization for large-scale networks based on multi-signal implications

    Masayuki Yuguchi, Kazutoshi Wakabayashi, Takeshi Yoshimura

    págs. 2390-2397

    

  • Representations of multiple-output functions using binary decision diagrams for characteristic functions

    Hafiz-Hasan Babu, Tsutomu Sasao

    págs. 2398-2406

    

  • Exact minimization of free BDDs and its application to pass-transistor logic optimization

    Kazuyoshi Takagi, Horoshi Hatakeda, Shinji Kimura

    págs. 2407-2413

    

  • Internet-based hierarchical floorplan design

    Jiann-Horng Lin, Jing Yang Jou, Iris-Hui Ru Jiang

    págs. 2414-2423

    

  • An algorithm to position fictitious terminals on borders of divided routing areas

    Atsushi Kamoshida, Shuji Tsukiyama

    págs. 2424-2430

    

  • Schedule-clock-tree routing for semi-synchronous circuits

    Kazunori Inoue, Wataro Takahashi, Atsushi Takahashi

    págs. 2431-2439

    

  • Simplified routing procedure for a CAD-verified FPGA

    Takahiro Murooka, Atsushi Takahara, Toshiaki Miyazaki

    págs. 2440-2447

    

  • Efficient forward model checking algorithm for w-regular properties

    Hiroaki Iwashita, Tsuneo Nakata

    págs. 2448-2454

    

  • A partially explicit method for efficient symbolic checking of language containment

    Kiyoharu Hamaguchi, Michiyo Ichihara, Toshinobu Kashiwabara

    págs. 2455-2464

    

  • A technique for modelling dynamic reconfiguration with improved simulation accuracy

    Milan Vasilko, David Cabanis

    págs. 2465-2474

    

  • Fast instructiion cache simulation for hardware/software co-design

    Marcello Lajolo, Luciano Lavagno, Alberto Sangiobanni Vincentelli

    págs. 2475-2484

    

  • A proposition on floating gate neuron MOS macromodeling for device fabrications

    Tadahiro Achiai, Hiroshi Hatano

    págs. 2485-2491

    

  • RSPICE: a fast and robust timing simulator for digital MOS VLSI

    Xia Cai, Huanzhong Wang, Yaowei Jia

    págs. 2492-2498

    

  • A VLSI scan-chain optimization algorithm for multiple scan-paths

    Susumu Kobayashi, Masato Edahiro, Mikio Kubo

    págs. 2499-2504

    

  • Digital-controlled analog circuits for weighted-sum operations: architecture, implementation and applications

    Jie Chen, Gouliang Shou, Changming Zhou

    págs. 2505-2513

    

  • A high-speed, low-power phase frequency detector and charge-pump circuits for high frequency phase-locked loops

    Won-Hyo Lee, Sung-Dae Lee, Jun-Dong Cho

    págs. 2514-2520

    

  • A new single-clock flip-flop for half-swing clocking

    Young-Su Kwon, In Cheol Park, Chong Min Kyung

    págs. 2521-2526

    

  • Parallel test structure in latch based asynchronous pipeline

    Jing-Ling Yang, Chiu Sing Choy, Cheoing-Fat Chan

    págs. 2527-2529

    

  • A method of service interference detection with rule-based system and extended adjacency matrix

    Yoshio Harada

    págs. 2532-2537

    

  • Learning the balance between exploration and exploitation via reward

    Tetsuya Yoshida, Koichi Hori, Shinichi Nakasuka

    págs. 2538-2545

    

  • A compositional approach for constructing communication services and protocols

    Bhed Bahadur Bista, Kaoru Takahashi, Norio Shiratori

    págs. 2546-2557

    

  • Time complexity analisys of the minimal siphon extraction problem of petri nets

    Masahiro Yamauchi, Toshimasa Watanabe

    págs. 2558-2565