B. Mei, S. Vernalde
págs. 255-261
Scheduling and mapping of conditional task graph for the synthesis of low power embedded systems
D. Wu, B. M. Al-Hashimi
págs. 262-273
Masking the energy behaviour of encryption algorithms
H. Saputra, N. Vijaykrishnan
págs. 274-284
págs. 285-293
J. Dielissen, E. Rijpkema, J. van Meerbergen, A. Radulescu, K. Goossens
págs. 294-302
Z. Peng, P. Eles, P. Pop
págs. 303-312
Development and application of design transformations in ForSyDe
I. Sander, A. Jantsch
págs. 313-320
Behavioural specifications allocation to minimise bit level waste of functional units
M. C. Molina, José Manuel Mendías Cuadros
págs. 321-329
Dynamically increasing the scope of code motions during the high-level synthesis of digital circuits
A. Nicolau, R. Gupta, S. Gupta, N. Dutt
págs. 330-337
págs. 338-345
Delay defect diagnosis based upon a statistical timing model - the first step
L.-C. Wang, K.-T. Cheng, A. Krstic
págs. 346-354
Low-cost software-based self-testing of RISC processor cores
D. Gizopoulos, N. Kranitis, G. Xenoulis
págs. 355-360
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